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| Asynchronous digital time-division multiplexing system with distributed bus |
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| Method for executing overlays in an expanded memory data processing system |
| OF THE INVENTION FIG. 1 shows an Expanded Memory System (EMS). The system includes a one megabyte (... |
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| Robot program checking method |
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| Method of correcting machine position change |
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| Fault diagnosis apparatus and method for sequence control system |
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| Binary MOS ripple-carry parallel adder/subtracter and adder/subtracter stage suitable therefor |
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| System for controlling power distribution to customer loads |
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| Apparatus for controlling the time sequenced energization of a memory unit |
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Tri-statable bus with apparatus to drive bus line to first level and then second level for predetermined time before turning off
| Details |
Inventors: Bechtolsheim, Andreas;
Assignee: Sun Microsystems, Inc. (Mountain View, CA)
Primary Examiner: Lee; Thomas C.
Assistant Examiner: Geckil; Mehmet
Attorney, Agent or Firm: Blakely, Sokoloff, Taylor & Zafman
An improved high speed data transfer bus with virtual memory capability is disclosed. The bus has particular applications in computer systems which employ peripheral devices. The bus allows high speed data transfer through the use of a virtual memory scheme. Moreover, the present invention minimizes the number of lines required to implement the bus. The present invention also minimizes the amount of time a particular device is required to wait before it can access the bus and complete a data transfer. Moreover, the present invention employs control signals that are driven both active and inactive, facilitating interfacing the bus to low-power CMOS technology. |
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DETAILED DESCRIPTION An improved high speed bus with virtual memory capability is disclosed.
The bus has particular application in computer systems which employ peripheral devices.
The bus allows high speed data transfer through the use of a virtual memory scheme.
Moreover, the present invention minimizes the number of lines required to implement the bus.
The present invention also minimizes the amount of time a particular device is required to wait before it can access the bus and complete a data transfer.
The bus comprises a plurality of lines including address lines, data lines and various command or control lines.
A variety of data processing units, referred to as agents, are coupled to the bus.
A controller is provided which controls access to the bus by the agents.
A memory management unit (MMU) and a virtual address latch (VAL) are coupled to the bus to implement the virtual address scheme of the present invention.
During operation of the bus, data is transferred between agents over the bus.
A requesting agent asserts a virtual address over the data lines in the bus.
This virtual address is converted into a physical address by the MMU.
This physical address is applied to address lines in the bus.
The requesting agent asserts a predetermined sequence of control signals, and the receiving agent which is storing the data asserts the requested data over the data lines.
The present invention also employs s method of preventing deadlock conditions to occur during the operation of the bus.
If a requesting agent supplied a virtual address to the MMU and the MMU does not have the necessary translation data to generate a physical address, then the MMU will issue a "rerun" signal.
This signal allows the requesting agent to "back off" are temporarily suspend the pending data transfer process.
The MMU can then gain control of the bus and fetch the proper translation data.
After the MMU has obtained the necessary translation data, the data transfer process is resumed.
Without the rerun signal the MMU would be unable to gain control of the bus
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I/O Systems 
