Universal device for coupling a computer bus to a controller of a group of peripherals

DETAILED DESCRIPTION We claim: 1.
A universal device for coupling a computer bus of a computer to a controller of a group of peripherals connected to one another by a specific link to which the controller is physically connected, said universal device including: a microprocessor connected with at least one memory said microprocessor having an operating system, a controller interface for linkage with the controller enabling transfer of data defining frames and control blocks wherein said control blocks include command characters relating to the frames transferred to either the link or the bus, a double-port random-access buffer memory connected by way of a first bus to said controller interface and by way of a second bus to the computer bus via a specific interface of the computer, means for organizing transfer of data by the microprocessor between said controller interface and the double-port memory, and between the double-port memory and the computer bus, a direct memory access controller operatively connected between said double-port memory and the computer, said transfer of data being effected under control of said direct memory access controller, wherein conversion of control blocks of protocols used on the computer bus into those used on the link and vice versa is performed by the microprocessor, which enables a transfer of control blocks used on the link over an internal bus of the microprocessor to or from said controller interface.
2.
The universal coupling device of claim 1, wherein the double-port memory includes a paginated memory zone including a plurality of pages each with a plurality of lines, an address/line register, an address/page register, a serial output register connected to the second bus and defining a second port of the double-port memory, a first port being connected to the first bus, the paginated memory zone being addressed by the address/page register for addressing each of said plurality of pages and by the address/line register with respect to each of said plurality of lines of a predetermined page, the first bus and the second bus being connected to the address/page and address/line registers, respectively, by way of a combination circuit, the serial output register including pointer means for enabling transfer, one after another, of each of said plurality of lines of a page of the paginated memory zone