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Details
Inventors: Tenma, Tetsuya;
Assignee: Pioneer Electronic Corporation (Tokyo, JP)
Primary Examiner: Groody; James J.
Assistant Examiner: Vu; Kim Yen
Attorney, Agent or Firm: Sughrue, Mion, Zinn, Macpeak & Seas

A video signal processing circuit processes a digital video signal to provide a stereoscopic video signal which can be presented without flicker and without reduced recording time. Digital video fields are consecutively stored in three memories or storage location of a memory, each new field replacing the oldest one. The fields are stored at a first clock rate. The stored video is read out at twice the first rate with each successive pair of fields being read out twice.

DETAILED DESCRIPTION To solve the conventional problems mentioned above, an object of the present invention is to provide a video signal processing apparatus for providing a stereoscopic picture image by compressing a video signal read from the recording medium with respect to the time axis, wherein the stereoscopic image is produced without flicker and the recording/reproducing time of the medium is not shortened.
With the above object in mind, the present invention resides in a video signal processing apparatus comprising first clock generating means for generating a first clock signal having a predetermined frequency; second clock generating means for generating a second clock signal having a frequency which is an integral times said predetermined frequency where said integer is not less than two; analog-digital converting means for producing digital data according to a sampling value provided by sampling an input video signal by said first clock signal in a predetermined period; memories for at least three fields for supplying said digital data thereto; and memory control means for controlling said memories for at least three fields such that said digital data are sequentially written by said first clock signal to the respective fields of said memories for at least three fields, every data group corresponding to one field, and two data groups corresponding to two fields constituting one frame are respectively written to the two fields of said memories for at least three fields, and the two data groups corresponding to the respective two fields constituting a frame located by one before said one frame are sequentially read out repeatedly an integral number of times by said second clock signal.



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