Video signal memories
One object of the present invention is to provide a video signal memory in which data can be written at high speed. Another object of the present invention is to provide a video signal memory in which... Read More
Inventors: Hedley, David J.; David, Morgan W. A.;, Assignee: Sony Corporation (Tokyo, JP) |
Obtaining access to a two-dimensional portion of a digital picture signal
The invention provides a method of obtaining access to a two-dimensional portion of a digital picture signal, which signal comprises a plurality of digital words representing respective pixels which, ... Read More
Inventors: Virtue, Peter J.; Keating, Stephen M.; Hedley, David J.;, Assignee: Sony Corporation (Tokyo, JP) |
Devices, systems and methods for accessing data using a pixel preferred data organization
According to the invention, a processing system is provided operating on data words each having at least first and second portions. The processing system includes a memory bank having first and second... Read More
Inventors: Guttag, Karl M.; Simpson, Richard D.; Gove, Robert J.;, Assignee: Texas Instruments Incorporated (Dallas, TX) |
Technique for accessing and refreshing memory locations within electronic storage devices which need to be refreshed with minimum power consumption
This and additional objectives are accomplished by the various aspects of the present invention, wherein, briefly, according to a principle aspect, memory locations within the DRAM memory structure ar... Read More
Inventors: Hazanchuk, Asher; Movshovich, Aleksander M.;, Assignee: Zilog, Inc. (Campbell, CA) |
Display apparatus
The present invention has been attempted to solve the above-described problems, and therefore, has an object to provide a display apparatus capable of increasing the total amount of the information wi... Read More
Inventors: Hara, Zenichiro;, Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP) |
Video timing and display ID generator
The invention provides an improved video timing generator and display ID generator that function at high pixel clock rates using readily available random access memory. The invention eliminates the ne... Read More
Inventors: Hannah, Marc;, Assignee: Silicon Graphics, Inc. (Mountain View, CA) |
Digital recorder for processing in parallel data stored in multiple tracks
It is therefore an object of the present invention to provide a digital recorder which is designed to suppress the large-scale hardware structure and reduce the load of a CPU. It is another object of ... Read More
Inventors: Iizuka, Nobuo; Manabe, Hajime;, Assignee: Casio Computer Co., Ltd. (Tokyo, JP) |
System for executing, canceling, or suspending a DMA transfer based upon internal priority comparison between a DMA transfer and an interrupt request
An object of the present invention is to provide a data processing device capable of shortening the processing time for stopping the DMA transfer, by stopping the DMA transfer according to the control... Read More
Inventors: Satoh, Kohtaroh;, Assignee: NEC Corporation (Tokyo, JP) |
Photographic order matching method and apparatus
In accordance with the foregoing objects the invention contemplates an apparatus in which corresponding identifying codes are provided on an order envelope and undeveloped film prior to processing of ... Read More
Inventors: Budworth, Janice I.; Knull, Donald F.; Maginness, Maxwell G.;, Assignee: CX Corporation (Seattle, WA) |
Circuitry for transferring data from a data bus and temporary register into a plurality of input registers on clock edges
In accordance with the present invention, a floating point processor is provided which substantially eliminates or prevents the disadvantages and problems associated with prior floating point processo... Read More
Inventors: Gill, Michael C.; Darley, Henry M.; Chiu, Edison H.; Niehaus, Jeffrey A.;, Assignee: Texas Instruments Incorporated (Dallas, TX) |
Branch prediction and resolution apparatus for a superscalar computer processor
The present invention provides an apparatus and method for improving the performance of superscalar pipelined computers using branch prediction. The described embodiment has two instruction processing... Read More
Inventors: Grochowski, Edward T.; Alpert, Donald B.; Mills, Jack D.; Weiser, Uri C.;, Assignee: Intel Corporation (Santa Clara, CA) |
Compressed Instruction format for use in a VLIW processor
OF THE PREFERRED EMBODIMENT FIG. 1a shows the general structure of a processor according to the invention. A microprocessor according to the invention includes a CPU 102, an instruction cache 103, an... Read More
Inventors: Jacobs, Eino; Ang, Michael;, Assignee: Philips Electronics North America Corporation (N.Y., NY) |
Apparatus for formatting a digital signal to include multiple time stamps for system synchronization
The present invention relates to a system and apparatus for inserting differential time codes or count values in a compressed video signal for developing synchronization of an intermediate layer of si... Read More
Inventors: Zdepski, Joel W.;, Assignee: RCA Licensing Corporation (Princeton, NJ) |
Synchronization and error detection in a packetized data stream
In accordance with the present invention, a method is provided for achieving synchronization and detecting errors in a data stream carrying successive packets of k information bits and r synchronizati... Read More
Inventors: Heegard, Chris; King, Andrew J.; Lovely, Sydney; Kolze, Thomas J.;, Assignee: General Instrument Corporation of Delaware (Chicago, IL) |
Liquid crystal display and a manufacturing method thereof
It is a primary object of the present invention to provide a liquid crystal display to which defects such as wiring fractures of the scanning signal line at the intersection of the scanning signal lin... Read More
Inventors: Kim, Sang-soo; Jang, In-sik; Kim, Dong-gyu; Song, Jun-ho; Park, Woon-yong;, Assignee: Samsung Electronics Co., Ltd. (Kyungki-do, KR) |
Method and apparatus for dynamic detection and routing of non-uniform traffic in parallel buffered multistage interconnection networks
It is therefore an object of the present invention to provide a multistage processor-memory interconnection network which alleviates congestion by confining the non-uniform part of the traffic to one ... Read More
Inventors: Chalasani, Suresh; Varma, Anujan M.;, Assignee: International Business Machines Corporation (Armonk, NY) |
Method and apparatus for creating a multiprocessor verification environment
This invention relates to a method and apparatus for creating a multiprocessor verification environment. The environment allows the Central Processor Unit (CPU) to be bypassed/excluded to allow the da... Read More
Inventors: Kreulen, Jeffrey Thomas; Mandyam, Sriram Srinivasan; O'Krafka, Brian Walter; Salamian, Shahram; Raghavan, Ramanathan;, Assignee: International Business Machines Corporation (Armonk, NY) |
Asynchronous sample pulse generator
These and other problems are resolved in accordance with the inventive principles to be described herein in relation to a pulse generator for generating pulse signals for sampling data bits asynchrono... Read More
Inventors: Hotchkiss, LaVerne Charles;, Assignee: Bell Telephone Laboratories, Incorporated (Murray Hill, NJ) |
Data synchronization
OF THE PREFERRED EMBODIMENT Referring now in detail to FIGS. 1 and 2, FIG. 1 shows the configuration of the equipment for recording, and FIG. 2 shows the configuration during playback. The same data ... Read More
Inventors: Dickens, John D.;, Assignee: The Commonwealth of Australia (AU) |
Therapeutic subliminal imaging system
The invention relates to portable systems for implementing behavior modification therapy wherein a subliminal message is added to a preexisting supraliminal message and the combined image is displayed... Read More
Inventors: Dwyer, Jr., Joseph J.; White, Loy R.; Haggerty, Matthew K.; Purbrick, John A.;, Assignee: Sub-Tv Limited Partnership (Newton Junction, NH) |
Trinary bus communication system
This invention presents a method and means of electrically communicating trinary digital information over two lines. The two lines can be a bus means comprising a pair of lines terminated at at least ... Read More
Inventors: Costello, John F.;, Assignee: |
High speed data transfer over twisted pair cabling
In accordance with the teachings of the present invention, a method is provided for transmitting data packets, grouped as data octets, over a LAN having a central hub linked to each of a plurality of ... Read More
Inventors: Albrecht, Alan; Goody, Steven H.; Spratt, Michael P.; Curcio, Jr., Joseph A.; Dove, Daniel J.; Jedwab, Jonathan; Crouch, Simon E.;, Assignee: Hewlett-Packard Company (Palo Alto, CA) |
Programming logic device with test-signal enabled output
In accordance with one aspect of the present invention, there is provided a programmable logic device including a plurality of programmable elements arranged in the form of an array and at least one f... Read More
Inventors: Takata, Akira; Fujii, Koichi;, Assignee: Ricoh Co., Ltd. (Tokyo, JP) |
Programmable combinational logic circuit
The invention provides a programmable logic circuit which is capable of providing any selected combinational logic function of a plurality of input logic signals, a particular logic function being est... Read More
Inventors: Baltus, Peter G.; Ligthart, Michael M.;, Assignee: North American Philips Corporation (New York, NY) |
Apparatus and method for providing a cache memory unit with a write operation utilizing two system clock cycles
It is an object of the present invention to provide an improved data processing unit. It is another object of the present invention to provide an improved cache memory unit in a central processing sub... Read More
Inventors: Stewart, Robert E.; Flahive, Barry J.; Keller, James B.;, Assignee: Digital Equipment Corporation (Maynard, MA) |
Dynamic random access memory arrangements having WE, RAS, and CAS derived from a single system clock
One object of the present invention is to provide an improved means of deriving control signals for a DRAM. Another object of the present invention is to provide a DRAM arrangement in which control si... Read More
Inventors: Collins, Mark C.;, Assignee: Sony Corporation (Tokyo, JP) |
Power saving sense amplifier that mimics non-toggling bitline states
According to the invention, a sense amplifier selectively prevents formation of the current branch if a constant signal is desired at the sense amplifier output line, i.e. a non-toggling state wherein... Read More
Inventors: Lee, Napoleon W.;, Assignee: Xilinx, Inc. (San Jose, CA) |
Communication multiplexer sharing a free running timer among multiple communication lines
A data processing system includes a central processing unit, a main memory and a communication subsystem, all coupled in common to a system bus. The communication subsystem includes a number of device... Read More
Inventors: Yu, Kin C.; Goss, Gary J.;, Assignee: Honeywell Information Systems Inc. (Waltham, MA) |
Method of operating an extension FIFO in another device when it is full by periodically re-initiating a write operation until data can be transferred
The present invention provides a protocol by which physically separated first-in, first-out (FIFO) memories may be made to operate as a single FIFO. In one case, one FIFO will write data to the other.... Read More
Inventors: Lohmeyer, Michael G.;, Assignee: National Semiconductor Corporation (Santa Clara, CA) |
Clock synchronous serial information receiving apparatus receiving reliable information even when noise is present
The invention was devised to solve the above problems, and it is an object thereof to provide a clock synchronous serial information receiving apparatus capable of receiving data normally when noise i... Read More
Inventors: Suzuki, Katsunori; Hata, Masayuki;, Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP) |
I/O Systems 
