System and method for enabling pointers to be passed from computer programs written using computer programming languages that do not support pointers
Having thus described our invention, what we claim as new and desire to secure by letters patent is: 1. A method performed by an application representing a computer program executing in a computer sys... Read More
Inventors: Wang, I-Shin Andy; Sharp, Frederick Thomas; Wu, Rita Shiao-yuan; Ng, John Shek-Luen; Hwang, Kuo-Wei; Chen, David Y.;, Assignee: International Business Machines Corp. (Armonk, NY) |
Digital copier enabling setting of a plurality of copying conditions in a single setting operation before copying is initiated
The present invention has been achieved in the light of such circumstances. An object of the present invention is to provide a digital copier which enables an operator to easily set a plurality of cop... Read More
Inventors: Nakajima, Akio; Muramatsu, Hideo;, Assignee: Minolta Camera Kabushiki Kaisha (Osaka, JP) |
System for data transfer across asynchronous interface
Briefly, the present invention includes a bridge with an input data register and multiple interface registers in one clock domain that can transfer data packets to a second clock domain. The use of mu... Read More
Inventors: Williams, David P.; Sutter, Stephen;, Assignee: Unisys Corporation (Blue Bell, PA) |
Data storage system
In accordance with one feature of the present invention, a computer/disk storage system interface is provided having disk controller, CPU controller, and cache memory printed circuit boards connected ... Read More
Inventors: Leshem, Eli;, Assignee: EMC Corporation (Hopkinton, MA) |
Stored program logic system using a common exchange circuit
What is claimed is: 1. A stored program logic system for use with a plurality of peripheral equipments comprising: a data memory (1) having a plurality of addressed fields (4) for storing processable ... Read More
Inventors: Anizan, Pierre;, Assignee: Telefonaktiebolaget L M Ericsson (Stockholm, SW) |
Magnetic memory organization
FIG. 1 shows a schematic diagram of an illustrative embodiment 10 of this invention. The memory comprises a layer 11 of magnetic material in which magnetic bubbles can be moved. Such a layer typicall... Read More
Inventors: Bonyhard, Peter I.;, Assignee: Bell Telephone Laboratories, Incorporated (Murray Hill, NJ) |
Device for controlling the radiating output of a semiconductor laser
It is an object of the present invention to provide a device for controlling the radiating output of a semiconductor laser, the device being of a reduced cost since it includes a photodetector of a re... Read More
Inventors: Shibata, Isamu; Kanmoto, Yoshiaki;, Assignee: Ricoh Co., Ltd. (Tokyo, JP) |
Electronic apparatus with memory backup system
Accordingly, an object of the invention is to provide an electronic apparatus capable of exactly deciding, during interruption of power supply thereto, validity of data retained in a memory with the a... Read More
Inventors: Imaizumi, Mamoru;, Assignee: Brother Kogyo Kabushiki Kaisha (Nagoya, JP) |
Compressed image virtual editing system
The present invention allows for pixel level manipulation of images that remain in a compressed form. In an image compression system using a typical image compression scheme, a pointer array is provid... Read More
Inventors: Miller, Robert F.; Blonstein, Steven M.;, Assignee: Ricoh Company, Ltd. (Tokyo, JP); Ricoh Corporation (Menlo Park, CA) |
Pseudo-concurrent access to a cached shared resource
A method and apparatus is disclosed for efficiently controlling the access to a cached shared resource such as dynamic random access memory (DRAM). The access is effected in a pseudo-concurrent manner... Read More
Inventors: Vanka, Subbarao; Ahmad, Abid;, Assignee: Intel Corporation (Santa Clara, CA) |
Interface module for telephone lines
OF THE INVENTION 1. Architecture of the Basic Module FIG. 1 is a schematic diagram of the architecture of two identical modules 10 and 10' in accordance with the invention. Module 10 includes two lin... Read More
Inventors: Froment, Jean-Claude; Pantani, Jean-Pierre; Verhaeghe, Michel;, Assignee: International Business Machines Corp. (Armonk, NY) |
Digital copier operable with external storing medium
It is, therefore, an object of the present invention to provide a digital copier having an external storing device of the type using an inexpensive storing medium. It is another object of the present ... Read More
Inventors: Sakata, Seiji; Harada, Tamotsu; Ito, Norifumi; Hayashi, Masayuki; Yoshimura, Tsuyoshi; Koinuma, Nobuyuki;, Assignee: Ricoh Company, Ltd. (Tokyo, JP) |
Image communication apparatus
It is an object of the present invention to improve an image communication apparatus in consideration of the above-mentioned problems. It is another object of the present invention to provide an image... Read More
Inventors: Hirai, Nobuyuki;, Assignee: Canon Kabushiki Kaisha (Tokyo, JP) |
Facsimile/telephone controller
OF THE INVENTION FIGS. 1a and 1b show a line sensing relay 14 and a double pole single throw latch relay 16 coupled between a telephone line 10 and a facsimile machine 12. Latch relay 16 is capable o... Read More
Inventors: Greenstein, Harvey; Levinski, Charles B.; Newman, Edward; Persel, John M.; Widmann, David N.;, Assignee: Hecon Corporation (Eatontown, NJ) |
High-frequency selecting switch terminal
OF THE INVENTION Referring to FIGS. 1 and 2, it can be seen that the housing (1) is threaded (11) on it's outer surface so as to engage with the high frequency selecting switch. A fist ring rim (13) ... Read More
Inventors: Cheng, Yu Feng;, Assignee: |
High speed pipeline merge sorter with run length tuning mechanism
Accordingly, it is an object of the invention to provide a control data generator for a sort processor which requires no programs for generating the control data and is made of simple and inexpensive ... Read More
Inventors: Kitsuregawa, Masaru; Fushimi, Shinya;, Assignee: Mitsubishi Denki K.K. (Tokyo, JP) |
High speed pointer based first-in-first-out memory
One embodiment of a high-speed pointer-based FIFO memory system constructed in accordance with this invention is depicted in FIG. 4. FIG. 4 is a block diagram showing an N word dual RAM FIFO memory s... Read More
Inventors: Hoberman, Barry A.;, Assignee: Advanced Micro Devices, Inc. (Sunnyvale, CA) |
Circuits, systems and methods for preventing queue overflow in data processing systems
The principles of the present invention are preferably applied to circuits, systems, and methods for controlling the transfer of memory requests from an input queuing system to a memory unit. In parti... Read More
Inventors: Adkisson, Richard W.;, Assignee: Covex Computer Corporation (Richardson, TX) |
Polled FIFO flags
It is desirable to provide a FIFO memory device which has polled status flags. It is also desirable to poll the FIFO memory device multiple times during its operation to determine its current status. ... Read More
Inventors: Barringer, David;, Assignee: Cypress Semiconductor Corp. (San Jose, CA) |
Image forming system including interconnected and priority allocated image forming devices
The object of the present invention is to provide an image forming system characterized in (1) having a network of a plurality of digital copying machines interconnected with each other, and (2) that ... Read More
Inventors: Toda, Rieko;, Assignee: Sharp Kabushiki Kaisha (Osaka, JP) |
Method for allocating priorities to plurality of DMA engines for processing data packets based on bus phase and transactions status
The present invention provides a method and apparatus for processing data packets through direct memory access (DMA) in transferring data packets between a bus and an apparatus containing DMA engines.... Read More
Inventors: Ghodrat, Fataneh F.; Thomas, David A.;, Assignee: LSI Logic Corporation (Milpitas, CA) |
Method and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple processing system
A method for transferring data between bus agents in a computer system including a system bus operating at a system bus clock rate is described. The method includes the step of receiving a transaction... Read More
Inventors: Pawlowski, Stephen S.; MacWilliams, Peter D.; Wu, William S.; Schultz, Len J.;, Assignee: Intel Corporation (Santa Clara, CA) |
Advanced programmable interrupt controller
According to the present invention, a computer system includes an advanced programmable interrupt controller (APIC) in which an I/O APIC module is integrated in core logic circuitry coupled between a ... Read More
Inventors: Klein, Dean A.;, Assignee: Micron Electronics, Inc. (Nampa, ID) |
Low speed serial bus protocol and circuitry
OF THE PREFERRED EMBODIMENT Referring now to FIG. 1, the computer system C according to the preferred embodiment is generally shown. The computer system C includes a processor 100 such as a Pentium.R... Read More
Inventors: Murray, David E.; Wooten, David R.;, Assignee: Compaq Computer Corporation () |
Serial bus system for sending multiple frames of unique data
Accordingly, the present invention discloses a computer system including a processor, a memory device, a North bridge logic coupling the processor and memory device, and a PCI expansion bus coupled to... Read More
Inventors: Deschepper, Todd; DeLisle, David J.; Wunderlich, Russ;, Assignee: Compaq Computer Corporation (Houston, TX) |
Data routing using status-response signals
The present invention provides an apparatus and method for routing data between multiple bus devices organized in a switch based topology. In the switch based topology of the preferred embodiment, the... Read More
Inventors: Blackmon, Herman Lee; Drehmel, Robert Allen; Haselhorst, Kent Harold; Marcella, James Anthony;, Assignee: International Business Machines Corporation (Armonk, NY) |
Data and data strobe circuits and operating protocol for double data rate memories
What is claimed is: 1. A computer populated with a plurality of double data rate DRAMS including a controller, controller logic circuits, a system clock, and a memory containing a storage array, an in... Read More
Inventors: Rogers, Jim L.; Fiscus, Timothy E.;, Assignee: International Business Machines Corp. (Armonk, NY) |
Non-volatile, electrically erasable and reprogrammable memory element
We claim: 1. A non-volatile, electrically erasable and reprogrammable memory element comprising a single p-channel MOS transistor with a polycrystalline silicon floating gate capacitively coupled to a... Read More
Inventors: Gerber, Bernard; Fellrath, Jean;, Assignee: Centre Electronique Horloger SA (Neuchatel, CH) |
High speed processing flip-flop
A high speed processing flip-flop contains a header circuit and a pulse flip-flop circuit. The header circuit is a clock pre-processing circuit that generates clock pulses for operation of the pulse f... Read More
Inventors: Rogers, Alan C.;, Assignee: Sun Microsystems, Inc. (Mountain View, CA) |
Compact multifunction logic circuit
The invention is a multifunction logic circuit, offering low power operation and compact layout.... Read More
Inventors: Waller, William K.;, Assignee: Micron Technology, Inc. (Boise, ID) |
I/O Systems 
