Shape memory alloy optical fiber switch
In FIG. 1, a switch is shown as a double pole switch. That is, two sets of fibers are switched and released at the same time. However, this is not a limitation of the invention. In principle, any num... Read More
Inventors: Jebens, Robert W.;, Assignee: AT&T Bell Laboratories (Murray Hill, NJ) |
Semiconductor memory device with reduced inter-band tunnel current
Accordingly, it is a general object of the present invention to provide a semiconductor memory device which can satisfy the need described above. It is another and more specific object of the present ... Read More
Inventors: Eto, Satoshi;, Assignee: Fujitsu Limited (Kanagawa, JP) |
Circuitry and method for addressing global array elements in a distributed memory, multiple processor computer
OF INVENTION FIG. 2 illustrates in block diagram form a distributed memory computer 20, which implements the global addressing scheme of the present invention. As will be described in more detail bel... Read More
Inventors: Baber, Marc;, Assignee: Intel Corporation (Santa Clara, CA) |
Methods for diagnosing malfunctions in a disk drive
The present invention concerns methods used in disk drives for diagnosing malfunctions in the path by which data passes to and from the disk. The disk drive in which the methods of the present inventi... Read More
Inventors: Gershenson, Edward; Lemone, Louis A.; Lippitt, Mark C.;, Assignee: Data General Corporation (Westboro, MA) |
Gate array with bidirectional symmetry
The invention is an improvement in a CMOS gate array comprising a plurality of core cells. The core cells each include at least one P-type device and at least one N-type device arranged within the cor... Read More
Inventors: Angleton, Joseph L.; Gutgsell, Jeffery L.;, Assignee: Hughes Aircraft Company (Los Angeles, CA) |
Multiprocessor systems having distributed shared resources and deadlock prevention
FIG. 1 shows in block diagram a multiprocessor system in accordance with the present invention. The system comprises a plurality (for instance four) of central processing units or CPU 1, . . . 4. The... Read More
Inventors: Bagnoli, Carlo; Perrella, Guido; Majo, Tommaso;, Assignee: Honeywell Bull Italia S.p.A. (Caluso, IT) |
Split bus multiprocessing system with data transfer between main memory and caches using interleaving of sub-operations on sub-busses
It is therefore an object of the present invention to provide an improved data processing system. It is another object of the present invention to provide an improved data processing system having a p... Read More
Inventors: Shaffer, Stephen J.; Warren, Richard A.; Eggers, Thomas W.; Strecker, William D.;, Assignee: Digital Equipment Corporation (Maynard, MA) |
Memory access control circuit with automatic access mode determination circuitry with read-modify-write and write-per-bit operations
Therefore, an object of the present invention is to provide a memory access control circuit which determines an optimum memory access mode and performs the determined memory access mode without requir... Read More
Inventors: Ohuchi, Mitsurou;, Assignee: NEC Corporation (Tokyo, JP) |
Data driven information processing system using address translation table to keep coherent cache and main memories and permitting parallel readings and writings
Therefore, an object of the present invention is to provide a data driven information processing system allowing accurate read/write from and to the memory at high speed without increasing the circuit... Read More
Inventors: Okamoto, Toshiya;, Assignee: Sharp Kabushiki Kaisha (Osaka, JP) |
Cache memory having a read-modify-write operation and simultaneous burst read and write operations and a method therefor
Accordingly, there is provided, in one form, a cache memory having a plurality of memory cells, a word line decoding circuit, and column decoding logic. The word line decoding circuit is coupled to th... Read More
Inventors: Jones, Kenneth W.; Bader, Mark D.; Kahlich, Arthur D.;, Assignee: Motorola, Inc. (Schaumburg, IL) |
Apparatus and method for providing a transparent disk drive back-up
OF THE PREFERRED EMBODIMENT Having summarized various aspects of the present invention, reference will now be made in detail to the description of the invention as illustrated in the drawings. While ... Read More
Inventors: Gunderson, Dick;, Assignee: DuoCor, Inc. (Nevada City, CA) |
Method for preventing unauthorized modification of data in a device with a nonvolatile memory
It is accordingly an object of the invention to provide a method for preventing unauthorized data modification in a device with a nonvolatile memory, which overcomes the hereinafore-mentioned disadvan... Read More
Inventors: Pockrandt, Wolfgang; Schrenk, Hartmut;, Assignee: Siemens Aktiengesellschaft (Munich, DE) |
Method of reading digital data on magnetic tape
I have hereby invented how to read digital data written in the standard format on a magnetic tape, more quickly than heretofore in the face of possible errors that will occur in reading each tape fram... Read More
Inventors: Saitoh, Shuichi;, Assignee: TEAC Corporation (Tokyo, JP) |
Method and apparatus for synchronizing disk drive requests within a disk array
There is provided, in accordance with the present invention, a method and apparatus for generating a single request signal for a logical storage unit including all or a subset of all the disk drives w... Read More
Inventors: Jibbe, Mahmoud K.; McCombs, Craig C.;, Assignee: NCR Corporation (Dayton, OH) |
Method and apparatus for an enhanced computer system interface
It is therefore an object of the present invention to provide an improved interface, based in part on the proposed SCSI-2 standard, by which multiple-byte commands, messages, and/or status information... Read More
Inventors: Gajjar, Kumar; Shah, Kaushik S.; Trang, Duc H.;, Assignee: MTI Technology Corporation (Sunnyvale, CA) |
Data processing device having an expandable address space
In the aforementioned CPU, however, the address register has a length of 16 bits, and the memory to be referred to by the CPU has a capacity of 65,536 bytes (=2.sup.16 or 64 Kbytes). In the applicatio... Read More
Inventors: Mitsuishi, Naoki; Baba, Shiro; Nagayama, Hiromi; Hayashi, Tsutomu; Hayakawa, Yukihide;, Assignee: Hitachi, Ltd. (Tokyo, JP) |
Single-chip mircocomputer with clock-signal switching function which can disable a high-speed oscillator to reduce power consumption
It is, therefore, an object of the present invention to overcome the problem existing in the conventional arrangement and to provide an improved single-chip microcomputer. It is another object of the ... Read More
Inventors: Niijima, Shinji;, Assignee: NEC Corporation (Tokyo, JP) |
Apparatus and method for reading helically recorded tracks and rereading tracks as necessary
OF THE DRAWINGS A helical-scan drive system 10 for recording on and reading magnetic tape 12 is illustrated in FIGS. 1 and 2. A drum 14 is angularly oriented with respect to the edges and direction o... Read More
Inventors: Georgis, Steven P.; Pisciotta, E. Christopher;, Assignee: Exabyte Corporation (Boulder, CO) |
Tri-statable bus with apparatus to drive bus line to first level and then second level for predetermined time before turning off
An improved high speed bus with virtual memory capability is disclosed. The bus has particular application in computer systems which employ peripheral devices. The bus allows high speed data transfer ... Read More
Inventors: Bechtolsheim, Andreas;, Assignee: Sun Microsystems, Inc. (Mountain View, CA) |
Method of compactly storing digital data
This invention provides a method of storing digital data in a compact manner which includes the steps of sequentially entering a plurality of digital data entries into a first shift register having a ... Read More
Inventors: Mussler, James M.; Neuner, James A.;, Assignee: Westinghouse Electric Corp. (Pittsburgh, PA) |
Method, device and microprocessor for selectively compressing video frames of a motion compensated prediction-based video codec
OF A PREFERRED EMBODIMENT A video sequence consists of individual images, or frames, of video data which are two dimensional representations of a three dimensional scene. A frame of video at time ins... Read More
Inventors: Banham, Mark R.; Brailean, James C.; Levine, Stephen N.; Katsaggelos, Aggelos K.; Schuster, Guido M.;, Assignee: Motorola (Schaumburg, IL); Northwestern University (Evanston, IL) |
Bus control for small computer system interface with transfer indication preceding final word transfer and buffer empty indication preceding receipt acknowledgement
Accordingly, it is an object of the present invention to provide a SCSI bus control which has overcome the above mentioned defect of the conventional one. Another object of the present invention is to... Read More
Inventors: Sugiyama, Yukinori;, Assignee: NEC Corporation (Tokyo, JP) |
Universal device for coupling a computer bus to a controller of a group of peripherals
We claim: 1. A universal device for coupling a computer bus of a computer to a controller of a group of peripherals connected to one another by a specific link to which the controller is physically co... Read More
Inventors: Pardillos, Jacky; Ravaux, Paul;, Assignee: Bull S.A. (Paris, FR) |
Display interface system using buffered VDRAMs and plural shift registers for data rate control between data source and display
The present invention elates to a method and apparatus for permitting computer graphics systems designed to work with cathode ray tube displays to greatly expand their range of pixel resolution and in... Read More
Inventors: McCord, Donald G.;, Assignee: |
Monitoring plural process control stations
We claim: 1. A monitoring system for process controllers with error recognition and compensation in a monitoring function comprising: a plurality of self monitoring process control stations, each incl... Read More
Inventors: Hess, Wilfried; Buxmeyer, Erwin; Ziegler, Wolfgang; Tremmel, Gerd R.; Barthol, Arthur;, Assignee: Hartmann & Braun AG (Frankfurt, DE) |
Arbitration circuitry for deciding access requests from a multiplicity of components
We claim: 1. In a data-handling system with a multiplicity n=2.sup.m of components of different ranks served by a common data bus alternatively accessible by said components in an order of precedence ... Read More
Inventors: Capizzi, Giuseppe N.; Melgara, Marcello;, Assignee: CSELT Centro Studi E Laboratori Telecomunicazioni S.p.A. (Turin, IT) |
Paged memory management unit which locks translators in translation cache if lock specified in translation table
Accordingly, it is an object of the present invention to provide a mechanism which allows a paged memory management unit to determine automatically from a field in each page descriptor in the translat... Read More
Inventors: Keshlear, William M.; Cohen, Robert B.;, Assignee: Motorola, Inc. (Schaumburg, IL) |
Ensuring data integrity by locked-load and conditional-store operations in a multiprocessor system
In accordance with one embodiment of the invention, a high-performance processor is provided which is of the RISC type, using a standardized, fixed instruction size, and permitting only a simplified m... Read More
Inventors: Sites, Richard L.; Witek, Richard T.;, Assignee: Digital Equipment Corporation (Maynard, MA) |
Multiplexing communication card and scanning method for run-in testing
i The present invention provides a multiplexing communication card and scanning system for testing and monitoring the test results of many PC's using a single host computer and monitor. The invention ... Read More
Inventors: Chan, Wai-Yip T.;, Assignee: Acer Incorporated (Taipei, TW) |
Fixture for motor controller power substrate and motor controller incorporating
In accordance with a first aspect of the invention, a fixture is provided for securing conducting pins to a power substrate module of the type including a rectifying circuit for converting alternating... Read More
Inventors: Wieloch, Christopher J.;, Assignee: Allen Bradley Company, Inc. (Milwaukee, WI) |
I/O Systems 
