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Arrangement-for-receiving-numerical-data-comprising-a-circuit-for-recognizing-the-start-of-packets

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Arrangement for receiving numerical data, comprising a circuit for recognizing the start of packets

Details

Inventors: Guenot, Andre; Cantou, Christian J. R.;
Assignee: U.S. Philips Corporation (New York, NY)
Primary Examiner: Groody; James J.
Assistant Examiner: Kostak; Victor R.
Attorney, Agent or Firm: Briody; Thomas A., Haken; Jack E., Barschall; Anne E.

Arrangement for receiving numerical data transmitted in the form of multiplexed packets in the video channel of a television transmission system, particularly comprising a circuit for recognizing data whose output signal (V) is used to authorize the transfer of the data signal (D) from a demodulator to a demultiplexer by means of an switching circuit (16a). The circuit (160) for recognizing the data comprises a D flip-flop (31) receiving the data signal (D), an exclusive-OR gate (33) whose inputs receive the data signal (D) and the output signal (D') of the D flip-flop (31) and which supplies from its output a signal (DX) applied to the input of a synchronous control module (32) which stores a given sequence of successive states of its input (36) during the opening period of a time window generated by a window generator (34) and which supplies the recognition signal (V) for authorizing the transfer when the said sequence of successive states is essentially a sequence of high states. Application: reception of data transmitted by means of a system such as Antiope, Ceefax or Nabts.

DETAILED DESCRIPTION The invention has for its object to provide an arrangement for receiving data, comprising a circuit for recognizing data which has a very good performance in the presence of noise signals at its input and which is also capable of easily adapting to different standards.
According to the invention an apparatus for receiving digital data of the type described in the opening paragraph is characterized in that the data recognition circuit comprises a D flip-flop, an exclusive-OR gate, a time window generator and a synchronous control module.
The apparatus is further characterized in that the data signal supplied by the demodulator is applied to the data input of the D flip-flop and to one of the inputs of the exclusive-OR gate.
The output signal of the D flip-flop is applied to the other input of the exclusive-OR gate.
The output signal of the exclusive-OR gate is transmitted to the input of the synchronous control module which stores a sequence of given states of its input during the opening period of the time window and which supplies from its output the signal for recognizing the start of the packets when the sequence of successive states is essentially a sequence of "1" states (high states).
As soon as the data clock is synchronized on the first bits of the bit synchronizing burst, the output signal of the exclusive-OR gate has, in synchronism with the data clock, "1" states for a reception of bits which succeed one another in a regular alternation of 1 and 0.
Consequently the synchronous control module can supply from its output a very reliable signal for recognizing the start of the packet.
For this purpose it is sufficient that this control module which can be realized in different forms, stores a sequence of successive states of its input during the time interval determined by the opening of the time window and supplies from its output an authorization signal on the condition that this sequence of successive states corresponds to a sequence of states all of which are 1 or only has a limited number of 0 states among a majority of 1 states

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