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CCD imager with photodetector bias introduced via the CCD register
| Details |
Inventors: Kosonocky, Walter F.;
Assignee: RCA Corporation (Princeton, NJ)
Primary Examiner: Rubinson; Gene Z.
Assistant Examiner: Brinich; Stephen
Attorney, Agent or Firm: Tripoli; Joseph S., Haas; George E., Limberg; Allen L.
An infrared charge-coupled-device (IR-CCD) imager uses an array of Schottky-barrier diodes (SBD's) as photosensing elements and uses a charge-coupled-device (CCD) for arranging charge samples supplied in parallel from the array of SBD's into a succession of serially supplied output signal samples. Its sensitivity to infrared (IR) is improved by placing bias charges on the Schottky barrier diodes. Bias charges are transported to the Schottky barrier diodes by a CCD also used for charge sample read-out. |
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DETAILED DESCRIPTION FIG.
1 shows a stylized representation of a portion 5 of a semiconductor imager of the infrared focal plane array, charge-coupled-device type.
Such an imager is commonly constructed on a monolithic silicon substrate.
FIG.
1 presents portion 5 of such an imager, assuming one to be viewing the "top" surface of the substrate, on which surface CCD gate electrode structures and Schottky barrier diode structures are disposed.
IRFPA/CCD imagers conventionally receive IR radiation from a direction such that it first impinges upon the top surface of the imager.
Gate electrode structures 15, 22, 24, 26, 28 repose in a first polysilicon layer; gate electrode structures 17, 21, 23, 25, 27, 29, in a second polysilicon layer.
The semiconductor imager includes at least one linear array 10 of Schottky barrier diode infrared detector elements; a plurality of parallelled straight-line linear arrays are customary in a planar array of radiation detector elements.
Linear array 10 is shown in FIG.
1 to include Schottky barrier diode structures having "metal" (typically, platinum silicide or palladium silicide) cathodes 11 and 12 and the p-type substrate as a shared anode.
The diode structures in line array 10 are for the most part surrounded by n-type guard rings indicated by lower-left to-upper-right diagonal shading.
That is, except at the left where n+ type diffusions, 13 and 14 indicated by upper-left-to-lower-right diagonal shading, are placed to ohmically contact cathodes 11 and 12 to offshoots 31 and 32 of a buried CCD channel 19.
The guard ring and ohmic contacts 13, 14 etc.
extend under the edges of the metal cathodes 11, 12 etc.
as indicated by the dashed lines in the peripheral portions of the cathodes.
A first-layer-polysilicon gate electrode structure 15 responds to potential pulses supplied by a multiple-pole switch control 16 to selectively reduce a barrier potential induced in the semiconductor substrate at the left sides of the diode structures in array 10.
A second-layer-polysilicon gate electrode structure 17 is biased (by means now shown) to provide channel stop between the diode structures in array 10 and along the right sides of those structures
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Image Analysis 
