Echo suppression circuit

DETAILED DESCRIPTION What is claimed is: 1.
An echo suppression circuit comprising an adder having an input means for receiving a signal having an echo, a control signal input, and an output means for providing a signal with at least a reduced echo; a delay device having an input coupled to said adder output means, a control signal input means for controlling the time delay thereof, and an output; and an automatic echo polarity correction circuit having an input coupled to said delay device ouptut, a first output means coupled to said adder control signal input for supplying a correction signal thereto, and a second output means coupled to said delay device control signal input means for supplying an echo position dependent control signal thereto for automatically adjusting the delay time thereof to the proper value.
2.
An echo suppression circuit as claimed in claim 1, wherein the echo polarity correction circuit comprises a multiplying circuit having a first input coupled to said output of the delay device and a second input; and further comprising an echo residual amplitude measuring circuit having an input coupled to the output of the adder circuit and an output coupled to said multiplier second input; said multiplier having an output from which the correction signal is obtained.
3.
An echo suppression circuit as claimed in claim 2, wherein said echo polarity correction circuit further comprises a correction signal polarity detector having an input coupled to said multiplier output and an output, a sign correction switch having a control signal input coupled to said correction signal polarity detector output and a signal input; and a control signal generator coupled to said switch signal input.




Description:
The invention relates to an echo suppression circuit wherein an output of a delay device having a delay time controllable by means of an echo-position independent control system is coupled to an input of an adder circuit for applying a correction signal thereto, this adder circuit having a further input for supplying a video signal in which the echo must be suppressed and an output which is coupled to an output of the echo suppressor circuit