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 Equalizer for the correction of digital signals

Details
Inventors: Tamburelli, Giovanni;
Assignee: CSELT - Centro Studi e Laboratori Telecomunicazioni S.P.A. (Turin, IT)
Primary Examiner: Safourek; Benedict V.
Assistant Examiner:
Attorney, Agent or Firm: Ross; Karl F., Dubno; Herbert

An equalizer designed to correct both precursor and postcursor distortion in signal samples periodically obtained from a train of digital symbols comprises two parallel circuit branches each including a delay line preceded by a linear upstream filter for postcursor suppression in the case of the first branch and precursor suppression in the case of the second branch. A decision stage in parallel with the delay line of the first branch works into a nonlinear downstream filter delivering a precursor-correcting signal to an adder which also receives precorrected earlier signals from the two delay lines. A second decision stage connected to an output of the adder feeds back to that adder a postcursor-correction signal via another nonlinear downstream filter. The purged signal emitted by the second decision stage may be subjected to additional filtering and precursor/postcursor correction with the aid of another adder and a third decision stage provided with a further feedback loop.

DETAILED DESCRIPTION I claim: 1.
An equalizer for eliminating the effects of postcursor and precursor interference from a periodically sampled train of incoming digital signals, comprising: receiving means connected to a transmission path carrying said incoming signals; a first circuit branch connected to said receiving means, said first branch including first upstream filter means for converting a given signal sample into a first linearly prefiltered signal with at least partial suppression of postcursor effects, first threshold means connected to said first upstream filter means for deriving a first quantized pulse from said first prefiltered signal, first downstream filter means connected to said first threshold means for generating a precursor-compensating signal from said first quantized pulse, and first delay means connected in parallel with said first threshold means to said first upstream filter means for emitting a first retarded signal corresponding to said first prefiltered signal; a second circuit branch connected in parallel with said first circuit branch to said receiving means, said second branch including second upstream filter means for converting said given signal sample into a second linearly prefiltered signal with at least partial suppression of precursor effects, said second branch further including second delay means connected to said second upstream filter means for emitting a second retarded signal corresponding to said second prefiltered signal, the retardations introduced by said first and second delay means being identical and exceeding by one sampling period a lag introduced by the series combination of said first threshold means and said first downstream filter means; summing means with inputs connected to said first and second delay means and to said first downstream filter means for receiving said first and second retarded signals and said precursor-compensating signal therefrom; second threshold means connected to said summing means for deriving a second quantized pulse from the combination of signals received by said summing means; and second downstream filter means connected in a feedback loop between an output of said second threshold means and a further input of said summing means for delivering thereto a postcursor-compensating signal, derived from said second quantized pulse, with a delay of one sampling period



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