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 Gate-turn-off thyristor failure detecting circuit

Details
Inventors: Seki, Nagataka; Koike, Shunichi; Watanabe, Yukio;
Assignee: Tokyo Shibaura Denki Kabushiki Kaisha (JP)
Primary Examiner:
Assistant Examiner:
Attorney, Agent or Firm:

A gate-turn-off thyristor failure detecting circuit includes a detector which detects an off-gate signal for a gate-turn-off thyristor and a current level detector which compares the signal with a predetermined value and produces an output signal indicative of the failure of the gate-turn-off thyristor.

DETAILED DESCRIPTION It is therefore an object of this invention to provide a GTO thyristor failure detecting circuit capable of detecting a failure of a GTO thyristor at the gate circuit thereof without any modifications in the main circuit, and of detecting failures that occur in any one of a group of interconnected GTO thyristors.
According to this invention, a gate-turn-off thyristor failure detecting circuit comprises a pulse amplifier for amplifying an off-gate signal, a pulse transformer having primary and secondary windings, the primary winding being connected to the pulse amplifier, a gate pulse synthesizing circuit for producing a gate pulse which is applied to a gate of the gate-turn-off thyristor, the gate pulse synthesizing circuit being connected to the secondary winding of the pulse transformer, means for detecting a signal flowing through the primary winding of the pulse transformer, and means for comparing the output signal from the detecting means with a predetermined value for producing a signal indicative of the failure of the gate-turn-off thyristor.
The accompanying drawings, which are incorporated in, and constitute a part of, this specification, illustrate two embodiments of the invention and, together with the description, serve to explain the principles of the invention.



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