Integrated systolic architecture for decomposition and reconstruction of signals using wavelet transforms

DETAILED DESCRIPTION OF THE INVENTION FIG.
1 shows a systolic array for computing a forward Discrete Wavelet Transform FIG.
1 shows an input xi 100 which is a single N-bit integer or floating point value from an input sequence representing discrete samples of an input signal that is to be encoded.
Though not specifically mentioned, all inputs and outputs are of the precision/type of the input.
Further, the various adders, multipliers and registers discussed can be readily designed by one skilled in the art depending upon the precision/type required.
In order for the array shown in FIG.
1 to be initialized, inputs x.
sub.
1, x.
sub.
2, x.
sub.
3, and x.
sub.
4 must first propagate through the delay elements 110, 112, 114, and 116.
Thereafter, for every x.
sub.
i 100 that is input, two outputs will be generated by the array.
These two outputs are shown in FIG.
1 as a.
sub.
i-4 150, which is the low frequency sub-band (LFS) output and, c.
sub.
i-3 160, which is the high frequency sub-band (HFS) output.
Each of the basic processing cells which compose the array are comprised of an adder and a multiplier and produce two sets of intermediate outputs.
The first set of intermediate outputs, L.
sub.
0 from cell D.
sub.
0 121, L.
sub.
1 from cell D.
sub.
1 122, L.
sub.
2 from cell D.
sub.
2 124, L.
sub.
3 from cell D.
sub.
3 126, and L.
sub.
4 from cell D.
sub.
4 128, are added by adder 130 to generate the LFS values a.
sub.
i-4 150.
Likewise, the second set of intermediate outputs, M.
sub.
1 from cell D.
sub.
1 122, M.
sub.
2 from cell D.
sub.
2 124, M.
sub.
3 from cell D.
sub.
3 126, and M.
sub.
4 from cell D.
sub.
4 128, are added together by adder 140 to generate the HFS values c.
sub.
i-3 160.
To generate the first HFS output c.
sub.
0, which occurs at i=3 (i=0,1,2 .
.
.
), the first four clock cycles and, consequently, the first three intermediate outputs, L.
sub.
1, L.
sub.
2, and L.
sub.
3 are required.
On the next clock cycle, at i=4, the LFS output a.
sub.
0 will be generated and observed.
Thus, the outputs a.
sub.
i-4 150 and c.
sub.
i-3 160 are observed alternately at the trailing edges of even and odd clock cycles