Load and store instructions which perform unpacking and packing of data bits in separate vector and integer cache storage

DETAILED DESCRIPTION The problems outlined above are in large part solved by a multimedia extension unit (MEU) of the present invention.
The MEU hereof embodies hardware components, and software instructions which optimally operate those components.
The MEU is added to an existing processor to more efficiently perform multimedia-type operations.
Thus, the MEU functions as a DSP, but more specifically as a high performance DSP necessary for achieving real time data compression.
The MEU can perform multiple operations within a single instruction cycle and therefore is particularly useful in performing repetitive, sequential operations found in MPEG, JPEG, DVI, Indeo and H.
320 compression systems.
The ability to perform multiple operations is contingent upon aligning numerous operands at select moments upon particular partitions within a partitioned arithmetic logic unit (ALU).
Thus, the MEU embodies hardware components which can arrange operands in response to specific operand routing instructions.
To carry out operand routing, the MEU employs, inter alia, three components: a partitioned ALU, an operand routing unit (ORU), and a series of partitioned registers.
The ALU is partitioned into vectors, each of which can perform a separate and independent operation from the other vectors.
The ORU aligns a series of operands on respective partitions of the vector ALU so that an operation can be performed on each operand concurrent with operations on other operands.
The operands are provided from registers.
Each register is partitioned into a series of vectors, classified as either slots or sub-slots.
Each slot or sub-slot contains sufficient bit locations to store an operand.
Operand routing is responsive to numerous multimedia-type instructions unique to the MEU.
The multimedia-type instructions, or "vector instructions", are decoded to the ORU as well as to each vector of the ALU.
Those instructions not only ensure that multiple operands are properly aligned to respective partitions of the ALU, but also serve to perform various data compression algorithms in a more efficient manner