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Details
Inventors: Wang, Naxin;
Assignee: Sony Corporation (Tokyo, JP); Sony Electronics, Inc. (Park Ridge, NJ)
Primary Examiner: Mai; Tan V.
Assistant Examiner:
Attorney, Agent or Firm: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.

Methods and apparatus for performing a fast two-dimensional inverse discrete cosine transform (IDCT) in a media processor are disclosed. A processor receives discrete cosine transform data and combines, in a first stage, the discrete cosine transform data with a first set of constants. In a media processor with a partitioned SIMD architecture, the discrete cosine transform data and first set of constants may be combined, for example, by multiplying the at least one input component with a first set of constants using a complex multiplication instruction. The output is transposed in a second stage and combined with constants in a third stage to obtain the pixel information of an image.

DETAILED DESCRIPTION Methods for performing a two-dimensional inverse discrete cosine transform consistent with this invention comprise stages performed by a processor.
A processor receives at least one input component representing discrete cosine transform data and combines, in a first stage, the at least one input component with a first set of constants.
The input data and first set of constants may be combined, for example, by multiplying the at least one input component with a first set of constants using a complex multiplication instruction.
The output is transposed in a second stage and combined with constants in a third stage.
Furthermore, an IDCT apparatus consistent with the present invention comprises an input means, a memory, at least one circuit, and an output means.
The input means receives at least one input component representing discrete cosine transform data.
The memory stores a first and second set of constants.
The at least one circuit combines the input components with the constants in a first stage, transposes the output data, and combines the transposed first-stage output data with the second set of constants in a third stage.
The circuit means may comprise, for example, a means for multiplying the at least one input component with a first set of constants using a complex multiplication instruction.
The output means for outputting output components representing pixel information of an image.



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