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Home Image Analysis Motion-estimation-processor-for-a-digital-video-encoder

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 Motion estimation processor for a digital video encoder

Details
Inventors: Boice, Charles E.; Curley, Lawrence D.; Kaczmarczyk, John M.; Ngai, Agnes Y.; Stein, Charles J.;
Assignee: International Business Machines Corporation (Armonk, NY)
Primary Examiner: Britton; Howard
Assistant Examiner:
Attorney, Agent or Firm: McGuireWoods LLP, Steinberg, Esq.; William H.

A digital video encoder system having a motion estimation processor, and an interface to the motion estimation processor. The motion estimation processor includes a reference memory interface, and inverse quantization processor, an inverse discrete cosine transform processor, and a motion estimation processor unit including a hierarchal search unit. The motion estimation processor is utilized generating temporally compressed datastreams, that is, I-P and I-P-B datastreams.

DETAILED DESCRIPTION OF THE INVENTION The invention relates to MPEG and HDTV compliant encoders, including scalable MPEG and HDTV compliant encoders, and encoding processes.
The encoding functions performed by the encoder include data input, spatial compression, motion estimation and compensation, macroblock type generation, data reconstruction, entropy coding, and data output.
Spatial compression includes discrete cosine transformation (DCT), quantization, and entropy encoding.
Temporal compression includes intensive reconstructive processing, such as inverse discrete cosine transformation, inverse quantization, and motion compensation.
Motion estimation and compensation are the temporal compression functions.
Spatial and temporal compression are repetitive functions, including memory fetching and writing, searching, comparing, and basic logic and arithmetic functions, all with or cumulatively resulting in high computational requirements.
More particularly the invention relates to a processor, for example, a scalable processor, for performing spatial and temporal compression including discrete cosine transformation, quantization, entropy encoding, motion estimation, motion compensation, and prediction, and even more particularly to a motion estimation processor within the system for accomplishing temporal compression.
The processor system of the invention has an I-frame only video encoder module with a Discrete Cosine Transform processor, a quantization unit, a variable length encoder, a FIFO buffer, and a compressed store interface, for generating an I-frame containing bitstream.
For IPB bitstreams the system further includes the motion estimation processor (MEPROC) of the invention with a reference memory interface, motion estimation and compensation capability, inverse quantization, and inverse discrete cosine transformation, and motion compensation means.
The system can be in the form of a single integrated circuit chip, or a plurality of integrated circuit chips.
The first compression step is the elimination of spatial redundancy, for example, the elimination of spatial redundancy in a still picture, that is, an "I" frame picture



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