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Multiple field of view calibration plate having a reqular array of features for use in semiconductor manufacturing
| Details |
Inventors: Michael, David; Wallack, Aaron;
Assignee: Cognex Corporation (Natick, MA)
Primary Examiner: Font; Frank G.
Assistant Examiner: Stafira; Michael P.
Attorney, Agent or Firm: Weinzimmer; Russ
A multiple field of view calibration plate is provided both for coordinating multiple fields of view of a plurality of cameras so as to facilitate determining the distance between features on a semiconductor wafer, each feature being disposed within a different field of view, and for correcting image distortion within each field of view. The multiple field of view calibration plate is particularly suited for use in semiconductor manufacturing, and includes a substantially rigid dimensionally-stable substrate having a systematic array of features that are sized such that more than one of the features can fit within a field of view. The array is of a spatial extent such that more than one of the fields of view are substantially filled with the features. Also, the systematic assay of features is characterized by a distribution density suitable for correcting image distortion within a field of view. The systematic array can be a regular array, each feature being separated from each nearest neighboring feature by an equal distance. Alternatively, the separation between neighboring features is a function of position on the substrate, so that given the relative location of two neighboring features, their position on the substrate can be deduced In addition, the substrate includes more than one landmark, each landmark being located at one of a plurality of possible camera positions, where the possible camera positions are of known relative position, so as to facilitate determining the distance between features each disposed within a different field of view. |
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DETAILED DESCRIPTION An article of manufacture is provided for use in a multi-camera machine vision system wherein each of a plurality of cameras simultaneously acquires an image of a different portion of a semiconductor wafer.
The article of manufacture of the invention makes it possible to precisely coordinate the fields of view of the plurality of cameras so that accurate measurements can be performed across the fields of view to a precision of fractions of a millimeter.
The invention provides a framework for achieving both high resolution, as well as coverage of widely separated portions of a large scene.
The invention provides a common coordinate system when there is more than one field of view, allowing position information from each field of view to be related to position information from other fields of view.
In addition, the invention provides information interrelating the coordinate systems of multiple fields of view, with improved precision that facilitates use in many applications, without loss of accuracy due to image distortion effects.
According to the invention, an article of manufacture is provided both for coordinating multiple fields of view of a plurality of cameras so as to facilitate determining the distance between features on a semiconductor wafer, each feature being disposed within a different field of view, and for correcting image distortion within each field of view.
The article includes a substantially rigid dimensionally-stable substrate, such as a plate, having a plurality of image distortion calibration targets for correcting image distortion within a field of view, that are each located at a known relative position.
In a preferred embodiment, each calibration target includes a feature that indicates an origin of the calibration target.
Preferably, each calibration target is located so that it can be directly viewed by a camera, and there is a calibration target for each possible camera location.
In applications where viewing the perimeter of a semiconductor wafer is of interest, each calibration target is disposed on the substrate so the target can be in the field of view of a camera positioned to include a portion of the edge of the semiconductor wafer at run-time
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Image Analysis 
