Parallel propagating embedded binary sequence for parameterizing two dimensional image domain code patterns in two dimensional address space

DETAILED DESCRIPTION OF THE INVENTION While the invention is described in some detail hereinbelow with reference to certain illustrated embodiments, it is to be understood that it is not limited to those embodiments.
On the contrary, the intent is to cover all modifications, alternative, and equivalents falling within the spirit and scope of the invention as defined by the appended claims.
A.
Self Clocking Glyph Codes Turning now the drawings, and at this point especially to FIG.
1, there is a more or less conventional self-clocking glyph code pattern 21 which is composed of elongated slash-like marks or "glyphs" 22 and 23 that are written on a generally regular rectangular lattice of centers on a suitable recording medium 24.
Suitably, the glyphs 22 and 23 are printed by a printer (not shown) operating at 300 d.
p.
i.
-600 d.
p.
i.
to write 4 pixel.
times.
4 pixel-7 pixel.
times.
7 pixel representations of the glyphs 22 and 23 on regularly spaced centers that are distributed widthwise and lengthwise of the recording medium 24 to produce the rectangular code pattern 21.
The glyphs of these fine grain glyph code patterns are not easily resolved by the unaided human eye when the code patterns are viewed under standard lighting conditions and at normal reading distances, so the code pattern 21 typically has a generally uniform gray scale appearance.
Nevertheless, the glyph code is still capable of effectively communicating machine readable digital information.
To carry out this function, the glyphs 22 and 23 usually are titled to the left and right, at about +45.
degree.
and -45.
degree.
with respect to the longitudinal dimension of the recording medium 24 to encode binary "1's" and "0's", respectively, as shown at 25.
B.
The Relative Phase of Parallel Propagating Embedded Maximal Length Bit Sequences as a Spatial Address Parameter FIGS.
2-8 diagramatically illustrate image domain address spaces which are constructed by embedding multiple instances of one (FIGS.
3 and 6) or two (FIGS.
2, 4, 5, 7 and 9) maximal length bit sequences ("Z" in FIGS