Process of compressing a succession of digital data and device for carrying out the same

DETAILED DESCRIPTION OF THE DRAWINGS FIG.
1 represents the block diagram of a compression circuit of a succession of words representing the pixels of an image.
The words of 8 bits are present in the parallel form and are applied to an input E to undergo a compression while the digital data resulting from this compression are registered in series in a buffer memory 7.
This memory is linked up to a mass storage 8 (magnetic disk system, for example), and repeated readings of the buffer memory allow to supply or "feed" the mass storage 8.
The purpose of the compression is to accelerate the image acquisition rhythm, despite a relatively slow transfer rhythm between memories 7 and 8.
As mentioned herein-above, the compression process consists essentially in memorizing, not the words of 8 bits representing the pixels, but the difference between the successive pixels, by using a code of variable length.
The input E is thus connected to an input Xn of the processing circuit 2 which will be described herein-below and to register 1 forming a memory the output of which is connected to an input X.
sub.
n-1 of processing circuit 2.
This latter circuit thus receives at any moment on its two inputs the value of a pixel and that of the preceding pixel.
The inputs E, Xn, X.
sub.
n-1 are parallel inputs of 8 bits (i.
e.
each presenting 8 lead-in terminals) and register 1 has parallel inputs and parallel outputs, also in 8 bits.
In the figures, each parallel connection is conventionally represented by a single wire cut by an oblique stroke next to which is indicated the number of bits of the said connection.
Circuit 2 comprises a parallel output C (16 bits) supplying the data (the code) to be registered, coded and "formatized" as well as a parallel output L (4 bits) supplying a representative data of the length of the code appearing simultaneously at output C.
Output L is applied to an input of a sequencer 4 comprising 3 clock outputs S1, S2 and S3 respectively connected to control three registers of 8 bits, 3,5 and 6