Self-correcting serial baud/bit alignment

DETAILED DESCRIPTION It is therefore a general purpose of the present invention to provide a more efficient USART than was heretofore possible.
It is another object to provide a USART in which the microcode is not burdened with the responsibility of establishing received data synchronization, nor is it responsible for re-establishing synchronization if the data is momentarily corrupted.
The objects and benefits are achieved by providing a circuit arrangement which synchronizes a received bit stream with a generated clock.
The resulting bit stream is then monitored to determine changes in the bit pattern.
If there is no change in the bit pattern for a predetermined number of bits or within a set bit time, a control signal is generated and is used to reset a synchronization latch.
Thereafter, the receiver is synchronized to the incoming bit stream.
More particularly, the circuit arrangement includes a Digital Phase Lock Loop (DPLL) that generates clock pulses.
Preferably, the clock pulses are positioned at the center of the baud cell.
A latch (L1) synchronizes the serial data stream with the clock pulses and generates a sampled serial data stream (D.
sub.
R).
Latch (L2) delays D.
sub.
R and outputs a delayed serial data stream (B.
sub.
R) which is gated with D.
sub.
R through an Exclusive (X) or (XOR) gate.
If D.
sub.
R =B.
sub.
R, the output from the "XOR" gate is low (that is, 0) and the synchronization latch (L3) is reset via the "And/OR" logic circuit means "AORI.
" The output from "AORI" is gated by an AND gate to provide a decoded data clock.
The combinational logic circuits "XNOR" and "AOR2" are gated with appropriately derived control signals to provide the decoded data.
The decoded data is clocked through latch (L4) by the data clock.
The resulting clock data is now available for use by the USART.
The foregoing features and advantages of the invention will be more fully described in the accompanying drawings, in which: