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Signal-processing-system-having-reduced-memory-space

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Signal processing system having reduced memory space

Details

Inventors: Fadavi-Ardekani, Jalil;
Assignee: AT&T Corp. (Murray Hill, NJ)
Primary Examiner: Couso; Yon J.
Assistant Examiner:
Attorney, Agent or Firm: Fox; James H.

A signal processing system includes means for performing a logic function on a multi-dimensional array of information stored in a memory. Typically, the memory stores two-dimensional video information (pixels), and the logic function is a discrete cosine transform (DCT), or other linear operation. The logic function is performed on both rows and columns of the information. In the prior art, this has required two memory spaces, so that information could be written into one memory while being read out of another memory. In the present invention, a single memory space is used to transpose the information between row and column format, by performing a read-modify-write operation on each memory location in a specified sequence.

DETAILED DESCRIPTION I have invented a technique for signal processing that transposes row and column information in a single memory array.
In this technique, the information that is written into the memory array is supplied in a given format (e.
g, column-wise).
However, the memory array is read out in specified address sequences that provide the information in another format (e.
g.
, row-wise).
After each memory location in the array is read out, the information for the next read operation is immediately written into that location.
The specified address sequences may be determined using modulus arithmetic based upon the dimensions of the array.

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