Teletext decoder arrangements

DETAILED DESCRIPTION What is claimed is: 1.
A teletext decoder arrangement comprising a plurality of data acquisition circuits, a memory having a capacity for storing a large number of acquired pages in separate memory chapters, first addressing means for addressing the chapters individually and second addressing means for addressing byte locations in each chapter, which teletext decoder arrangement is characterised in that said first addressing means includes a register file having a number of word locations in each of which any one of a plurality of different pointer bytes can be stored, said word locations being addressable, to read out a pointer byte stored therein, by respective word addresses each of which pertains to a respective one of the data acquisition circuits, each of said pointer bytes identifying according to its bit values a respective memory chapter and each being usable when read out from a word location to select its memory chapter for the storage therein of a page acquired by the appertaining data acquisition circuit, the arrangement further including processor means for identifying the word location concerned by its word address and for determining the bit values of the pointer byte in that word location.
2.
A teletext decoder arrangement as claimed in claim 1, characterised in that the register file comprises four 4-bit word locations each for storing any one of sixteen different chapter memory pointer bytes.
3.
A teletext decoder arrangement as claimed in claim 1, characterised in that the register file comprises four 8-bit word locations each for storing any one of two hundred and fifty six different chapter memory pointer bytes.
4.
A teletext decoder arrangement as claimed in claim 1, 2, or 3, characterised in that said processor means is further operable to list in a table register the identity of used memory chapters together with the page numbers of acquired pages which are stored therein.
5.
A teletext decoder arrangement as claimed in claim 4, characterised in that said processor means is operable to continuously update the table register when the arrangement is in use and the table register is interrogated by the processor means when a page request is made to determine whether the requested page has already acquired and stored in a particular memory chapter