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Television circuit arrangement for field and line frequency doubling and picture part magnification
| Details |
Inventors: Frencken, Peter H.; Raven, Johannes G.; Annegarn, Marcellinus J. J. C.;
Assignee: U.S. Philips Corporation (New York, NY)
Primary Examiner:
Assistant Examiner:
Attorney, Agent or Firm:
In a television circuit arrangement for field and line frequency doubling and picture part magnification (zooming), in order to obtain the frequency doubling, information is written, alternately, into two field memories (M1, M2) during a field period having line periods at a given writing speed (clock frequency fc), whereby the reading from the field memories takes place at twice the writing speed. For a picture part magnification to be carried out in a simple manner, a magnification control circuit (TG, S3, S4, S11, S12) having a clock signal change-over circuit (S3, S4) is provided, as a result of which during writing, a higher writing speed (clock frequency 2fc) than the said given writing speed (clock frequency fc) is used during a part of the field periods and of the line periods, which part is substantially inversely proportional to the ratio between the higher writing speed and the given writing speed. For intermittent writing, one or more change-over circuits (S11, S12) are provided at the memory signal inputs, which provides, besides a more effective information storage and an improvement of the picture quality, the possibility of movement detection and recursive signal processing for noise reduction. |
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DETAILED DESCRIPTION What is claimed is: 1.
A television circuit arrangement for field and line frequency doubling and picture part magnification, said television circuit arrangement comprising a signal input for receiving information and a signal output for supplying information; first and second field memories arranged in parallel between said signal input and said signal output, each field memory having a signal input, a signal output and a clock signal input; a write/read circuit having first means for coupling the signal input of said television circuit arrangement to the signal inputs of said first and second field memories, respectively, second means for coupling the signal outputs of said first and second field memories, respectively, to the signal output of said television circuit arrangement, and a clock signal source circuit coupled to said first and second coupling means and said clock signal inputs of said first and second field memories, respectively, said write/read circuit controlling writing of said information into said first and second field memories, respectively, during alternate field periods, each field period including line periods, for a writing time equivalent to a field period at a given writing speed, and reading of said information twice from said first and second field memories, respectively, during a field period following the field period in which said first and second field memories, respectively, are written, for a reading time equivalent to a field period at a reading speed which is substantially twice the writing speed; and a magnification control circuit, coupled to said first and second field memories and said write/read circuit, for providing said picture part magnification, characterized in that said magnification control circuit comprises a clock signal change-over circuit coupled to said clock signal source for selectively modifying the clock signals therefrom, whereby, during the writing of said information into said first and second field memories, the writing speed is selectively made higher than said given writing speed during a part of the field periods and of the line period in said writing time, which part is substantially inversely proportional to the ratio between said higher writing speed and said given writing speed
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Image Analysis 
