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Details
Inventors: Nishikawa, Ryuji;
Assignee: Sanyo Electric Co., Ltd. (Osaka, JP)
Primary Examiner: Gross; Anita Pellman
Assistant Examiner:
Attorney, Agent or Firm: Loeb & Loeb LLP

In an active matrix type liquid crystal display apparatus, a thin film transistor of staggered type is formed in the vicinity of the intersection of the gate line and the drain line. Moreover, in the above mentioned vicinity of the intersection of the drain line, a projection part extending in the longitudinal direction of the gate line is provided. This projection part functions essentially as the drain electrode. The confronting region, where the source electrode, the drain electrode and the projection part confront each other, is covered by the gate electrode constituting a part of the gate line. By providing the projection part in the drain line, and hence also forming the channel region in the confronting region of the source electrode and the projection part, this channel region becomes an isolated composition within the thin film transistor. Therefore, a parasitic channel is prevented from forming between the source electrode of the pixel on one side, and the drain electrode of another pixel on the other side, and this parasitic channel is prevented from conducting electricity.

DETAILED DESCRIPTION It is the object of the invention to provide a liquid crystal display apparatus having a structure which prevents the formation of the parasitic transistor between neighboring pixels across the drain line.
To realize the above object, an active matrix type liquid crystal display apparatus of the present invention comprises the following features.
First, the active matrix type liquid crystal display apparatus of the present invention comprises a plurality of pixel electrodes formed on a substrate in a matrix array, and drain lines formed between the columns of said pixel electrodes, gate lines formed between the rows of said pixel electrodes, insulation layers and semi-conductor layers, formed under said gate lines, and thin film transistors formed in the vicinity of each intersection of said drain lines and said gate lines.
Each of the thin film transistors comprises a source electrode section constituting a part of the pixel electrode, and a drain electrode section constituting a part of the drain line.
Each transistor further comprises a channel layer constituting a part of the semi-conductor layers, a gate insulation layer formed on the channel layer and constituting a part of the insulation layers, and a gate electrode section formed on the gate insulation layer, constituting a part of the gate line and formed by extending the gate line.
Further, the drain line comprises a projection part and the projection part is disposed in the vicinity of the joint of the gate electrode section.
Moreover, this projection part is formed within the region covered by the gate electrode or the gate line.
Also, the projection part is, for example extended along the longitudinal direction of the gate line and from the drain line.
Further, the gate line or the gate electrode is formed over the confronting region where the source electrode, and the drain electrode, as well as the projection part, are disposed facing each other, and in this confronting region, a channel region of the thin film transistor is formed



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