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Array with metal scan lines controlling semiconductor gate lines
| Details |
Inventors: Wu, I-Wei;
Assignee: Xerox Corporation (Stamford, CT)
Primary Examiner: Wojciechowicz; Edward
Assistant Examiner:
Attorney, Agent or Firm:
Array circuitry formed at the surface of a substrate includes M scan lines that cross N data lines. The array circuitry also includes cell circuitry connected to the mth scan line and the nth data line. The cell circuitry includes a component with a data lead for receiving signals from or providing signals to the nth data line. The cell circuitry also includes connecting circuitry with first and second semiconductor lines. The first semiconductor line has a channel between the nth data line and the data lead of the component. The second semiconductor line is connected to the mth scan line and crosses the first semiconductor line at the channel. Because the second semiconductor line is conductive, signals on the mth scan line control conductivity of the channel. The semiconductor lines can be polysilicon, and the scan lines can be aluminum. The component can include a capacitive element with one electrode under the (m+1)th scan line, part of which forms the other electrode of the capacitor. The channel can be under the nth data line, leaving the cell area free. The component can also include a light transmissive cell electrode in the cell area, and the array circuitry can be used in a display, with liquid crystal material positioned along the cell electrode. The display can also include peripheral circuitry outside the boundary of the array circuitry, connected to the scan lines and data lines. |
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DETAILED DESCRIPTION The invention addresses problems that affect arrays of circuitry formed on substrates. A two-dimensional (2D) array, for example, can include two sets of conductive lines extending in perpendicular directions, as illustrated by FIG. 3 of the Wu article described above. Each line extending in one direction can provide signals to a column of the array; each line extending in another direction can provide signals to a row of the array. Conventionally, each row-column position in a 2D array includes circuitry, sometimes called a "cell," that responds to or provides signals on the lines for the cell's row and column combination. Through one set of parallel lines, illustratively called "data lines," each cell receives or provides signals that determine or indicate its state. Through the other set of parallel lines, illustratively called "scan lines," each cell along a scan line receives a signal that enables the cell to receive signals from or to provide signals to its data line. The area of each cell that is bounded by data lines and scan lines, referred to herein as the "cell area," can serve as a transducer, providing or receiving signals to or from sources outside the array. In conventional arrays, each scan line provides a periodic scan signal that enables a component in each cell connected to the scan line to receive a signal from or provide a signal to its data line during a brief time interval of each cycle. Therefore, tight synchronization of the scan signals with signals on the data lines is critical to successful array operation. Also, the scan signals must maintain high quality transitions across an array. If a scan line has high resistance, its propagation delay is long, which causes signal distortion, preventing accurate signal synchronization and causing inaccurate loading or extraction of data. Some conventional techniques address the scan line resistance problem by using metal scan lines. But each cell's circuitry conventionally includes a semiconductor channel, and the conductivity of the channel is conventionally controlled by the scan signals, also referred to as "gate signals" by analogy to the gate of a transistor
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