Charge pump for word lines in programmable semiconductor memory array

DETAILED DESCRIPTION In the following description, the statement that a capacitive circuit or capacitor is "passive" is understood to mean that the capacitive circuit/capacitor is formed by passive conductive surfaces and dielectrics which do not include substantial junction and surface inversion layer areas which would otherwise induce carrier injection.
Unless stated otherwise, the term "conductive line" is understood to refer to word lines and bit lines.
The following description illustrates embodiments of the invention by way of example and not necessarily by way of limitation.
FIG.
1 shows a preferred pre-decoding/decoding circuit 20 of the present invention.
Circuit 20 comprises a NAND gate 22 serving as a word line pre-decoder.
Gate 22 has multiple address line inputs 24 and a single pre-decoder output 26.
Pre-decoder output 26 is selected (logic 0 level) when all inputs 24 are selected, and it is de-selected (logic 1 level) if any of inputs 24 is de-selected.
Pre-decoder output 26 is connected to an input of a word line decoder circuit 30.
Decoder circuit 30 comprises an enhancement p-channel device 32 and an enhancement n-channel device 34.
The sources of devices 32 and 34 are connected to pre-decoder output 26, and the drains of devices 32, 34 are connected to an internal decoder node 36.
The gates of devices 32, 34 are connected to external X and X decoder inputs, respectively.
The signals X and X are generated by a conventional multiple level decoding circuit, and are derived from X-address lines other than those used for inputs 24.
An enhancement p-channel device 38 has its source connected to Vcc=5V, its drain connected to node 36, and its gate connected to the X input.
Device 38 serves as a de-select device.
An inverter 40 has its input connected to node 36, and its output connected to a node 44.
Node 44 is connected to the common sources of an enhancement device 46 and a depletion (-1 V threshold) device 48.
The gates of devices 46 and 48 are connected to Vcc and to a PGM input, respectively