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 Composite dielectric passivation of high density circuits

Details
Inventors: Ahlburn, Byron T.;
Assignee: Texas Instruments Incorporated (Dallas, TX)
Primary Examiner: Dang; Trung
Assistant Examiner:
Attorney, Agent or Firm: Honeycutt; Gary, Grossman; Rene, Donaldson; Richard

A composite dieletric film for final passivation of an integrated circuit. First, plasma-enhanced TEOS oxide is deposited to a thickness of 2000 .ANG., followed by thermal O.sub.3 -TEOS oxide to a thickness of 8000 .ANG., and then silicon nitride to a thickness of 10,000 .ANG..

DETAILED DESCRIPTION What is claimed is: 1.
A method for the formation of a final passivation composite on an integrated circuit comprising the steps of: a) depositing an initial film of silicon oxide on the circuit by a plasma-enhanced decomposition of TEOS until said initial layer has a thickness of only 1,000 to 3,000 Angstroms, and terminating said deposition at that time; b) then depositing a second film of silicon oxide on said initial film, by reacting ozone with TEOS until said second film has a thickness of 6,000 to 10,000 Angstroms, and terminating said deposition at that time; and c) then depositing a final film of silicon nitride on said second film.
2.
A method as in claim 1 wherein the initial film is deposited at a temperature of 200 degrees C.
to 600 degrees C.
3.
A method as in claim 2 wherein the second film of silicon oxide is deposited at a pressure of 400 to 700 Torr.




Description:
FIELD OF THE INVENTION This invention relates to the deposition of a composite dielectric film as the final overcoat protection for an integrated circuit.
Improved mechanical and electrical characteristics are obtained.
BACKGROUND OF THE INVENTION As 16 Megabit DRAM devices move toward production, the requirements placed on dielectric films used for inter-metal isolation exceed the capabilities of traditional films and techniques.
First-level metal spaces as small as 0.
5 micron and metal thickness as great as 0.
9 micron are encountered.
For these dimensions standard deposition techniques such as plasma TEOS CVD (PETEOS) result in voids or sharply cusped seams between the leads.
These issues can be addressed by the use of spin-on glasses (SOG), but these films tend to crack and absorb and release water vapor and other gases, which interfere with subsequent processing.
Therefore, blanket etchback is often used to remove the SOG from the vicinity of vias.
Achieving good planarization using SOG techniques generally requires multiple coat/cure cycles and the surface planarity is generally degraded by the plasma loading effects during etchback



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