Interconnect architecture for field programmable gate array using variable length conductors

DETAILED DESCRIPTION According to one aspect of the invention, a repeatable structure is provided which includes a logic unit capable of receiving input signals from a plurality of input lines and providing a plurality of output signals on a corresponding plurality of output lines, the output lines of one logic unit being of more than one length.
The output lines of one logic unit extend past other logic units.
Provided periodically along each output line is a plurality of interconnection points (PIPs).
The PIPs allow the output lines to be connected to input lines of other logic units.
This combination of output lines of differing lengths and PIPs allows a user to connect logic units either to nearby logic units or to logic units some distance away.
According to another aspect of the invention, the number of PIPs which may be driven by one output line is approximately the same as the number of PIPs which may be driven by each other output line.
Most PIPs are buffered, that is, they comprise a buffer followed by a connector such as a transistor.
Providing an approximately equal number of buffered PIPs on each output line produces the benefit that signals which propagate a short distance on an output line have approximately the same delay as signals which propagate a longer distance on a longer output line.
According to yet another aspect of the invention, the frequency of PIPs decreases as distance from the originating logic unit increases.
This has the benefit of cooperating with software which tends to place interconnected logic in close proximity.
As another feature, the architecture can connect selected output lines to other output lines so that a signal path can be extended.
This feature eliminates the necessity for undedicated line segments used in conventional FPGAs, although it also can work with an embodiment which includes undedicated line segments.
A tile is a schematic drawing of a portion of a circuit in which elements and lines are positioned such that an array of tiles placed side by side shows electrical continuity across the tile boundaries between lines in adjacent tiles