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Details
Inventors: Masutani, Yuichi; Kobayashi, Kazuhiro;
Assignee: Mitsubishi Denki Kabushiki Kaisha (Tokyo, JP)
Primary Examiner: McPherson; John A.
Assistant Examiner:
Attorney, Agent or Firm: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.

The present invention provides a liquid crystal display apparatus with high reliability in which accuracy of a width of a comb-shaped electrode is improved in the plane, particularly, at a boundary of divisional exposure, display unevenness of the boundary portion of divisional exposure is reduced in a lateral direction electric field method, and provides a manufacturing method thereof. In the method of manufacturing the liquid crystal display apparatus of the present invention wherein the liquid crystal display apparatus is manufactured so that a counter electrode opposite to a pixel electrode is provided and an electric field whose direction is horizontal to the surface of a substrate is applied between the pixel electrode and the counter electrode and thus liquid crystal is driven, when a pixel section is exposed, the exposure is carried out repeatedly by using one mask so that the pattern is formed. Moreover, according to this manufacturing method, a liquid crystal display apparatus having high reliability, in which display unevenness at the boundary portion of divisional exposure is reduced, is obtained.

DETAILED DESCRIPTION EMBODIMENT 1 The following will describe a substrate of a TFT array according to EMBODIMENT 1 of the present invention and a method of manufacturing a liquid crystal display apparatus having the substrate.
First, a gate line 1 is formed by Al, Cr, Mo or W, or alloy mainly containing Al, Cr and Mo, or a laminated film made of them.
At this time, the gate line 1 and a counter electrode 5 are formed simultaneously.
At this time, in order to obtain reliability of a liquid crystal display apparatus, the stepper method is used as exposure in the photolithography process.
At this time, in order to prevent scattering of an electrode width due to a difference in dimension between masks from occurring, a pixel section 7 is exposed repeatedly by using one mask, and a terminal section 8 is exposed by using another mask.
FIGS.
1 and 2(a) to 2(b) show this exposing method.
FIG.
1 shows positions on the substrate of the TFT array where the exposure is carried out, and FIGS.
2(a) to 2(b) schematically show positions of masks 21 and 22 where the exposure is carried out.
As for the pixel section shown in FIG.
1, the portions A shown in FIG.
2(a) are exposed repeatedly, for example, four times.
As for the terminal section, the portions shown by portion B through I in FIG.
2(a) and FIG.
2(b), which are represented by portion B through I in FIG.
1, are exposed.
After a gate insulating film is formed on the whole surface, amorphous silicon 12 and amorphous silicon 13 including impurity are formed simultaneously.
When the amorphous silicon 12 and the amorphous silicon 13 with which impurity was doped are formed, exposure may be carried out by the method shown in FIGS.
1 and 2, but one panel including the terminal section is divided into not less than two, for example, four portions as shown in FIG.
3, and the respective patterns may be exposed by using different masks.
In the method shown in FIGS.
1 and 2(a) to 2(b), sixteen times of exposure is required, but when the exposure is carried out in a manner shown in FIG



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