Process for forming ultra-shallow source/drain extensions

DETAILED DESCRIPTION The present invention relates to a method of manufacturing an integrated circuit.
The method includes providing a gate structures, including a dummy spacer material from a portion of the substrate, removing the dummy spacer material, forming an amorphous region in the portion of the substrate, and providing dopants to the amorphous region to form an extension to a source or a drain.
Removing the dummy spacer material leaves an opening.
The amorphous region is formed in a substrate below the opening, and dopants are provided through the opening.
The present invention further relates to a method of manufacturing an ultra-large scale integrated circuit.
The circuit includes a plurality of field effect transistors having shallow source and drain extensions.
The method includes steps of removing a dummy spacer material from at least part of a gate structure on a top surface of a semiconductor substrate to form a first hole and a second hole, providing a semiconductor implant through the first hole and through the second hole, and providing a dopant implant through the first hole and through the second hole.
The dummy spacer material is provided as part of the gate structure.
The present invention further relates to a process for forming shallow source extensions and shallow drain extensions in a semiconductor substrate.
The process includes forming a plurality of gate structures on a top surface of the substrate, removing a pair of spacers from each of the gate structures, thereby exposing the top surface of the substrate, and providing a dopant through the exposed top surface of the substrate.
The dopant creates the shallow source extension and the shallow drain extension.