Apparatus and method for leadless packaging of semiconductor devices

DETAILED DESCRIPTION The present invention is directed to a leadless and interconnected semiconductor package.
The package includes a first semiconductor chip with a second semiconductor chip positioned on the first chip to form a vertically stacked package.
Each semiconductor chip further includes a plurality of bond pads disposed on an active surface of the chips that are electrically coupled to the active elements formed within each chip.
Interconnections between the bond pads on each chip are formed by metallized layers disposed on the package that extend between corresponding bond pads and join a plurality of castellations disposed along sides of the package to form a plurality of leadless input/output locations for the package.
In one aspect of the invention, the castellations include generally planar metallized portions extending downwardly to a lower surface of the package.
In another aspect, the castellations include semi-cylindrical metallized portions that project inwardly into sides of the package.
In a further aspect, a dielectric insulator is positioned between the first and second chips and positioned on a base of the package.
In still a further aspect, a semiconductor chip with a photosensitive device formed therein includes at least one optical layer positioned on the photosensitive device.
A plurality of bond pads are positioned on the chip that are electrically coupled to the photosensitive device on the chip.
Castellations extend outwardly from the bond pads to form a plurality of leadless input/output locations for the package.