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| Semiconductor device |
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Avalanche photodiode having a multiplication layer with superlattice
| Details |
Inventors: Yoo, Ji-Beom; Park, Chan-Yong; Kim, Hong-Man;
Assignee: Electronics and Telecommunications Research Institute (KR); Korea Telecommunication Authority (KR)
Primary Examiner: Jackson; Jerome
Assistant Examiner:
Attorney, Agent or Firm: Larson and Taylor
An avalanche photodiode in which a strained superlattice structure is used as a multiplication layer, comprising: an n.sup.+ type InP substrate; an n.sup.+ type InP epitaxial layer formed on a main surface of the substrate; an N type In.sub.1-x Al.sub.x As layer formed on the epitaxial layer; an n.sup.+ type In.sub.1-x Al.sub.x As layer formed on the N type In.sub.1-x Al.sub.x As layer, the n.sup.+ type In.sub.1-x Al.sub.x As layer having a relatively high impurity concentration more than the N type In.sub.1-x Al.sub.x As layer; the multiplication layer deposited on the n.sup.+ type In.sub.1-x Al.sub.x As layer, the multiplication layer having an In.sub.0.53 Ga.sub.0.47 As/In.sub.1-x Al.sub.x As superlattice structure; first and second p.sup.+ type In.sub.1-x Al.sub.x As layers laminated sequentially on the multiplication layer; an absorbing layer formed on the second p.sup.+ type In.sub.1-x Al.sub.x As layer, the absorbing layer being made of an In.sub.0.53 Ga.sub.0.47 As; a P type InP layer formed on the absorbing layer to reduce a surface leakage current; an In.sub.0.53 Ga.sub.0.47 As layer formed on the P type InP layer to be provided for an ohmic contact, and metal layers formed on an upper surface of the In.sub.0.53 Ga.sub.0.47 As layer and the other surface of the substrate, respectively. |
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DETAILED DESCRIPTION It is the object of the present invention to provide an avalanche photodiode in which an InAlAs/InGaAs superlattice structure is used as a multiplication layer in order to overcome the above-mentioned problems.
To achieve the object, an avalanche photodiode according to an aspect of the present invention comprising: an n.
sup.
+ type InP substrate; an n.
sup.
+ type InP epitaxial layer formed on a main surface of the substrate; an N type In.
sub.
1-x Al.
sub.
x As layer formed on the epitaxial layer; an n.
sup.
+ type In.
sub.
1-x Al.
sub.
x As layer formed on the N type In.
sub.
1-x Al.
sub.
x As layer, the n.
sup.
+ type In.
sub.
1-x Al.
sub.
x As layer having a relatively high impurity concentration more than the N type In.
sub.
1-x Al.
sub.
x As layer; a multiplication layer deposited on the n.
sup.
+ type In.
sub.
1-x Al.
sub.
x As layer, the multiplication layer having an In.
sub.
0.
53 Ga.
sub.
0.
47 As/In.
sub.
1-x Al.
sub.
x As superlattice structure; first and second p.
sup.
+ type In.
sub.
1-x Al.
sub.
x As layers laminated sequentially on the multiplication layer; an absorbing layer formed on the second p.
sup.
+ type In.
sub.
1-x Al.
sub.
x As layer, the absorbing layer being made of an In.
sub.
0.
53 Ga.
sub.
0.
47 As; a P type InP layer formed on the absorbing layer to reduce a surface leakage current; an In.
sub.
0.
53 Ga.
sub.
0.
47 As layer formed on the P type InP layer to be provided for an ohmic contact, and metal layers formed on an upper surface of the In.
sub.
0.
53 Ga.
sub.
0.
47 As layer and the other surface of the substrate, respectively.
In one embodiment, the epitaxial layer has about 1 to 3 .
mu.
m in thickness and is doped with an impurity concentration of approximately 1.
times.
10.
sup.
18 cm.
sup.
-3.
In another embodiment, the first P type In.
sub.
1-x Al.
sub.
x As layer has about 300 to 400 Angstroms and is doped with an impurity concentration of approximately 1.
times.
10.
sup.
18 cm.
sup.
-3.
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MEMS 
