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Flip-chip structure and method for high quality inductors and transformers
| Details |
Inventors: Raskin, Glenn D.; Marlin, George W.; Mitchell, Douglas G.;
Assignee: Freescale Semiconductor, Inc. (Austin, TX)
Primary Examiner: Chen; Kin-Chan
Assistant Examiner:
Attorney, Agent or Firm:
A structure and method for achieving a flip-chip semiconductor device having plated copper inductors (4), transformers (16), interconnect, and power busing that is electrically superior, lower cost, and provides for higher quality inductors as well as lower losses for on-chip transformers. Providing a solder dam (8, 24, 28) enables the fabrication of flip-chip solder bumps directly on to inductors and transformers. |
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DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT Referring to the Figures by characters of reference, FIG.
1 illustrates a flip-chip structure for an inductor fabricated within a microchip in accordance with a preferred embodiment of the present invention.
A wafer 2 is illustrated having an inductor 4 formed therein.
Inductor 4 is typically formed from electroplated copper over a titanium/tungsten (TiW) seed layer 6.
A region of dielectric material 8 is provided over wafer 2 and around inductor 4.
Solder bumps 10 are formed directly to inductor 4 thereby forming the flip-chip structure.
Solder bumps 10 are then bonded directly to a microchip package, or substrate pads, by reflowing the solder bumps 10 in a subsequent thermal process.
All bumps 10 are bonded to the package or substrate pads at the same time.
Dielectric layer 8 serves a variety of functions.
First, dielectric layer 8 serves to isolate inductor 4 and wafer 2 from exposure to corrosive moisture.
Further, dielectric layer 8 provides mechanical stress relief within the overall packaged semiconductor.
In a packaged semiconductor, a highly compressive mold compound is formed over wafer 2 on top of dielectric layer 8.
This high stress from compressive mold compound can damage glass layer 12.
Dielectric layer 8 functions to relieve the stress from compressive mold compound and protect glass layer 12.
As a result, dielectric layer 8 functions to protect the integrity of the overall packaged semiconductor.
Layer 8 also functions as stress relief in flip-chip applications where underfill is used between die and substrate.
It is desirable to have good adhesion between the underfill and dielectric in such applications.
Dielectric layer 8 also protects inductor 4 from damage.
During subsequent flip-chip processes, mechanical damage can occur to inductor 4.
In addition, the highly compressive mold compound forming the packaged semiconductor protective case can mechanically damage inductor 4.
Dielectric layer 8 forms a protective barrier around inductor 4 to shield against mechanical damage
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MEMS 
