Gate stack for high performance sub-micron CMOS devices

DETAILED DESCRIPTION A principle objective of the invention is to provide a gate electrode structure having sub-micron device feature lengths.
Another objective of the invention is to provide a gate electrode structure having sub-micron device feature lengths whereby scaling issues of the gate oxide of the device are addressed.
Yet another objective of the invention is to provide a gate electrode structure having sub-micron device feature lengths whereby air-gap spacers are combined with selected gate dielectrics.
A still further objective of the invention is to provide a gate electrode structure having sub-micron device feature lengths of increased drive current capability.
A still further objective of the invention is to provide a gate electrode structure having sub-micron device feature lengths of reduced parasitic capacitance impact.
In accordance with the objectives of the invention a new method is provided for the creation of sub-micron gate electrode structures.
A high-k dielectric is used for the gate dielectric, providing increased inversion carrier density without having to resort to aggressive scaling of the thickness of the gate dielectric while at the same time preventing excessive gate leakage current from occurring.
Further, air-gap spacers are formed over a stacked gate structure.
The gate structure consists of pre-doped polysilicon of polysilicon-germanium, thus maintaining superior control over channel inversion carriers.
The vertical field between the gate structure and the channel region of the gate is maximized by the high-k gate dielectric, capacitive coupling between the source/drain regions of the structure and the gate electrode is minimized by the gate spacers that contain an air gap.