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 High frequency analog transistors method of fabrication and circuit implementation

Details
Inventors: Davis, Christopher K.; Bajor, George; Beasom, James D.; Crandell, Thomas L.; Jung, Taewon; Rivoli, Anthony L.;
Assignee: Harris Corporation (Melbourne, FL)
Primary Examiner: Dutton; Brian
Assistant Examiner:
Attorney, Agent or Firm: Rogers & Killeen

A fabrication process for dielectrically isolated high frequency complementary analog bipolar and CMOS transistors. Polysilicon extrinsic bases, polysilicon emitters with sidewall spacers formed after intrinsic base formation provides high current gain, large emitter-to-base breakdown voltage, large Early voltage, and high cutoff frequency.

DETAILED DESCRIPTION The present invention relates generally to the manufacture of integrated circuits and more specifically to complementary bipolar transistors having high Early voltage, high frequency performance, and high breakdown voltage characteristics.
Evolution of these analog products parallels the industry trend for higher speed semiconductor devices and higher levels of functional integration.
Historically, device architectures have been characterized by deep device junctions and have not minimized lateral device geometries.
Furthermore, the limited variety of device types which can be fabricated with a given process has, in turn, limited the integration of analog and digital functions.
U.
S.
Pat.
No.
4,665,425 to Piotrowski teaches the fabrication of vertical complementary bipolar transistors in dielectrically isolated islands.
By forming vertical NPN and PNP transistors frequencies above 1 GHz have become achievable.
In order to attain higher frequency performance, it is necessary to decrease junction depths and lateral device dimensions.
Junction depths can be reduced with self-aligned polysilicon emitters and the emitter-to-extrinsic base spacing can be reduced with an interposing dielectric spacer.
A further advantage of polysilicon emitters is that they allow favorable trade-off is between current gain and Early voltage.
U.
S.
Pat.
No.
4,908,691 to Silvestri, et al.
discloses and exemplary high frequency BiCMOS process.
Vertical complementary bipolar transistors are formed in an integrated circuit having lateral dielectric isolation and junction bottom isolation.
It is an object of the present invention to provide a method of fabricating complementary bipolar transistors of still higher frequency.
Another object of the invention is to provide complementary bipolar transistors for high frequency analog applications characterized by increased current gain and Early voltage characteristics.
Still another object is to provide a method for manufacturing integrated circuits incorporating these higher performance complementary bipolar transistors



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