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 In-line wafer surface mapping

Details
Inventors: Yang, Wan-Cheng;
Assignee: Taiwan Semiconductor Manufacturing Company (Hsin-Chu, TW)
Primary Examiner: Pert; Evan
Assistant Examiner:
Attorney, Agent or Firm: Duane Morris LLP

A method and apparatus for the topographical profiling of a raw substrate is carried out during in-line processing of the substrate during which additional films and structures have been formed over the raw substrate surface. The method includes forming a dielectric film over the substrate surface and forming a metal film over the dielectric film. The structure is polished and monitored during various stages of the polishing operation. An interferometer is used to monitor the surface being polished and to distinguish between regions where metal remains and regions in which metal has been removed and the underlying dielectric material exposed. Topographical data, such as a substrate map, is generated by monitoring the time at which the metal film is removed from various spatial locations across the substrate. The substrate map may be generated during polishing, for in-line monitoring.

DETAILED DESCRIPTION FIG.
2 is a plan view that illustrates an uneven substrate surface of an exemplary substrate.
Alternatively stated, the substrate surface has a non-uniform topography.
The topography of the uneven surface is represented by plot 11 which is taken along arbitrary direction 12 in the exemplary embodiment.
The higher and lower sections in plot 11 correspond to raised and depressed sections of substrate 1, respectively, and are exemplary only.
Such information is conventionally gathered when substrate 1 is in raw form and prior to any of the processing operations have been performed upon the substrate 1.
A number of plots 11 may be taken at various locations and in various directions along the surface of substrate 1 to provide for the topographical mapping of the substrate.
FIG.
3 is a cross-sectional view of exemplary substrate 1.
Substrate 1 may be any of various substrates such as an N- or P-type silicon substrate, a gallium arsenide substrate, a sapphire substrate or other substrates commonly used in the semiconductor manufacturing industry.
Such substrates upon which semiconductor devices are to be formed, are also referred to as wafers in the semiconductor manufacturing industry.
Substrate 1 includes substrate surface 3 upon which semiconductor devices are to be formed.
Substrate surface 3 is uneven and includes raised sections 5 and depressed sections 7.
As shown in FIG.
2, substrate 1 is generally round and may include a diameter 9 that may be 4, 6, 8, 10 or 12 inches or greater, in various exemplary embodiments.
FIG.
4 shows the structure shown in FIG.
3, after layer 13 has been formed over surface 3 of substrate 1.
Layer 13 may consist of a single film or a plurality of films and one or more patterned layers may be included within layer 13.
For example, layer 13 may represent an interlevel dielectric (ILD) that covers a patterned polysilicon or other film that forms interconnect leads.
Layer 13 may also represent a film or plurality of films that have been polished using conventional methods



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