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Mechanical grating device |
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Reduced formation of asperities in contact micro-structures |
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Low Cu percentages for reducing shorts in AlCu lines |
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Avalanche photo diode with quantum well layer |
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Avalanche photodiode having a multiplication layer with superlattice |
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Staircase avalanche photodiode |
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Semiconductor photo detector containing crystalline amplification layer |
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Manufacture of MEMS structures in sealed cavity using dry-release MEMS device encapsulation
| Details |
Inventors: Carley, L. Richard;
Assignee: IC Mechanics, Inc. (Pittsburgh, PA)
Primary Examiner: Whitehead, Jr.; Carl
Assistant Examiner: Dolan; Jennifer M
Attorney, Agent or Firm: Greenberg Traurig, LLP
The disclosed fabrication methodology addresses the problem of creating low-cost micro-electro-mechanical devices and systems, and, in particular, addresses the problem of delicate microstructures being damaged by the surface tension created as a wet etchant evaporates. This disclosure demonstrates a method for employing a dry plasma etch process to release encapsulated microelectromechanical components. |
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DETAILED DESCRIPTION In general, the invention disclosed refers to gas phase release of any number of microstructure layers whose movement is independent or coupled and which are encapsulated in the thin film seal layer. However, in order to explain the invention, one specific embodiment will be described in detail below, namely a microstructure that can be utilized as a Z-axis accelerometer. This device consists of a paddle shaped MEMS microstructure anchored at one point by a thin supporting member such that it can move vertically within the sealed cavity. FIGS. 1-9 illustrate the sequence of steps comprising the fabrication of the proposed encapsulated integrated microstructure CMOS process. We start by obtaining or fabricating a silicon CMOS wafer 2 coated with a layer of silicon nitride 4 and having metal pads interfacing to the original CMOS integrated circuit 6, 8 and 10 present as shown. Openings appear in the silicon nitride layer 4 to allow access to metal pads 6 and 8. In the preferred embodiment, the metal pads would be aluminum, but may alternatively be copper or any other conductive material. To begin the fabrication process, a sacrificial layer 12 is deposited on top of the passivation layer of the standard CMOS wafer 2, which in this case is silicon nitride layer 4. The MEMS device fabrication steps are all performed at low temperature on top of the complete CMOS wafer 2, leaving the circuitry therein undisturbed. Cuts in the passivation layer 4 are left during the CMOS IC design and sacrificial layer 12 is removed over these cuts if access to the metal contacts is desired. The exposed metal contacts 6 and 8 are then used to make connections between the MEMS microstructure and the CMOS circuitry in silicon CMOS wafer 2 below. This is illustrated in FIG. 2A. In the preferred embodiment the microstructure may be composed of any metal, for example, Al, W, Ti, Ta, Cu, Ni, Mo, etc. , but in the preferred embodiment would be made of aluminum. The selection of material for a particular microstructure layer is dictated by two factors
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