Method for using disposable hard mask for gate critical dimension control

DETAILED DESCRIPTION A principal object of the present invention is to provide an effective and very manufacturable method of providing a necking-free and uniform critical dimension width for polysilicon across an uneven topography.
Another object of the present invention is to provide a method of critical dimension control which will not impact or disturb the final device characteristics.
A further object of the present invention is to provide a method of critical dimension control using a disposable hard mask.
In accordance with the objects of this invention a new method of controlling the critical dimension width of polysilicon by using a disposable hard mask is achieved.
A semiconductor substrate is provided wherein the surface of the substrate has an uneven topography.
A layer of polysilicon is deposited over the uneven surface of the substrate.
The polysilicon layer is covered with a spin-on-glass layer wherein the spin-on-glass material planarizes the surface of the underlying topography.
A semiconductor layer is deposited over the surface of the planarization layer to act as a hard mask wherein the semiconductor layer is opaque to actinic light.
The semiconductor layer is covered with a uniform thickness layer of photoresist.
The photoresist layer is exposed to actinic light wherein the semiconductor layer prevents reflection of the actinic light from its surface.
The photoresist layer is developed and patterned to form the desired photoresist mask for the polysilicon layer.
The semiconductor layer, the spin-on-glass layer, and the polysilicon layer not covered by the photoresist mask are anisotropically etched away to form polysilicon gate electrodes and interconnection lines.
The photoresist mask, the hard mask, and the spin-on-glass layer are removed to complete the formation of polysilicon gate electrodes and interconnection lines having uniform critical dimension in the fabrication of an integrated circuit.