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| Image sensor or LCD including switching pin diodes |
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| Semiconductor integrated circuit and method of making the same |
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Method of fabricating a complementary bipolar junction transistor
| Details |
Inventors: Nam, Dong-kyun; Bae, Sung-ryoul;
Assignee: Samsung Electronics Co., Ltd. (Gyeonggi-do, KR)
Primary Examiner: Dang; Trung
Assistant Examiner:
Attorney, Agent or Firm: Lee & Morse, P.C.
A method of fabricating a complementary bipolar junction transistor includes forming a polycrystalline silicon layer on an NPN bipolar junction transistor region and a PNP bipolar junction transistor region, respectively implanting an N-type impurity and a P-type impurity into the polycrystalline silicon layer, and then diffusing to respectively form an N-type emitter region and a P-type emitter region within a P-type base region and an N-type base region. By patterning the polycrystalline silicon layer, an N-type emitter electrode and a P-type emitter electrode are simultaneously formed. The polycrystalline silicon layer is used for simultaneously forming the N-type emitter electrode of the NPN bipolar junction transistor and the P-type emitter electrode of the PNP bipolar junction transistor by a single depositing and etching process. |
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DETAILED DESCRIPTION The present invention is therefore directed to a method of fabricating a complementary bipolar junction transistor, which substantially overcomes one or more of the problems due to the limitations and disadvantages of the related art.
It is a feature of an embodiment of the present invention to provide a method of fabricating a complementary bipolar junction transistor that simultaneously forms a P-type emitter electrode of a PNP bipolar junction transistor and an N-type emitter electrode of an NPN bipolar junction transistor.
It is another feature of an embodiment of the present invention to provide a method of fabricating a complementary bipolar junction transistor that forms a P-type emitter electrode of a PNP bipolar junction transistor and an N-type emitter electrode of an NPN bipolar junction transistor in a single deposit and etch process.
It is yet another feature of an embodiment of the present invention to provide a method of fabricating a complementary bipolar junction transistor in which a P-type emitter region of a vertical PNP bipolar junction transistor is formed as a shallow junction.
At least one of the above and other features and advantages of the present invention according to an aspect of the present invention may be realized by providing a method of fabricating a complementary bipolar junction transistor including, providing a substrate having a P-type base region and an N-type base region on active regions of a PNP bipolar junction transistor region and an NPN bipolar junction transistor region, forming a first polycrystalline silicon layer pattern having contact holes that partially expose surfaces of the P-type base region and the N-type base region, forming a second polycrystalline silicon layer on an entire surface of the silicon substrate having the first polycrystalline silicon layer pattern, the second polycrystalline silicon layer filling the contact holes, respectively forming an N-type emitter region and a P-type emitter region within the P-type base region and the N-type base region by implanting and diffusing an N-type impurity and a P-type impurity respectively into the second polycrystalline silicon layer of the NPN bipolar junction transistor region and the PNP bipolar junction transistor region, and simultaneously forming an N-type emitter electrode and a P-type emitter electrode by patterning the second polycrystalline silicon layer and the first polycrystalline silicon layer
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MEMS 
