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Lightweight solar module and method of fabrication |
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Device for one-sided etching of a semiconductor wafer |
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Method of fabricating solar cell with integrated interconnect
| Details |
Inventors: Glenn, Gregory S.;
Assignee: Spectrolab, Inc. (Sylmar, CA)
Primary Examiner: Weisstuch; Aaron
Assistant Examiner:
Attorney, Agent or Firm: Gudmestad; Terje, Denson-Low; W. K.
A pattern of current collection gridlines (24) is formed on a surface (20) of a photovoltaic wafer (12). An ohmic contact strip (28) is formed adjacent to an edge (12c) of the wafer (12) in electrical interconnection with the gridlines (24). Interconnect tabs (30) are integrally formed with the gridlines (24) and contact strip (28), extending away from the contact strip (28) external of the edge (12c) for series or parallel interconnection with other solar cells. The interconnect tabs (30) may have a stress reflief configuration, including a non-planar bend or loop. The wafer (12) initially has a first portion (12a) and a second portion (12b). A barrier layer (50) of photoresist or the like is formed on the second portion (12b). The grid (24) and contact strip (28) are formed on the first portion (12a) simultaneously with forming the interconnect tabs (30) over the barrier layer (50 ) on the second portion (12b) using photolithography and metal deposition. The barrier layer (50) is dissolved away, and the second portion (12b) is broken away from the first portion (12a), leaving the interconnect tabs (30) extending from the contact strip (28) external of the remaining first portion (12a) of the wafer (12). |
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DETAILED DESCRIPTION OF THE INVENTION Referring to FIGS. 1 and 2 of the drawing, a solar cell embodying the present invention is generally designated as 10, and is fabricated from a photovoltaic member in the form of a wafer 12 made of a semiconductive material such as silicon. Initially, the solar cell 10 may be processed together with a quantity of similar cells as a portion of a single wafer 12. Each cell 10 on the wafer 12 has a first portion 12a, and a second portion 12b which is illustrated in broken line. An edge 12c is defined between the first and second portions 12a and 12b. The wafer 12 further has an edge 12d opposite the edge 12c. As viewed in FIG. 2, the wafer 12 is fabricated into a photovoltaic structure using a diffusion process or the like so as to have a semiconductor junction 14 defined between differently doped regions 16 and 18. Irradiation of light on a first surface 20 of the wafer 12 causes liberation of charge carriers including electrons and holes in the region of the junction 14, which migrate toward the first surface 20 or a second surface 22 depending on their polarity. An electrically conductive pattern of current collection gridlines 24 is formed on the surface 20 for collection of charge carriers which migrate thereto. A similar pattern of gridlines or a continuous electrically conductive ohmic contact layer 26 is formed on the second surface 22 for collection of charge carriers of the opposite type. The gridlines 24 are formed as a metallization having a pattern, line thickness, and spacing selected to provide an optimal compromise between transmission of incident light into the wafer 12 and electrical current collection efficiency. The gridlines 24 are integrally formed in electrical interconnection with an ohmic contact strip 28 on the first portion 12a of the wafer 12 adjacent to the edge 12c. In accordance with an important feature of the present invention, electrically conductive interconnects which are illustrated as tabs 30 are formed integrally with the gridlines 24 and contact strip 28, and extend from the contact strip 28 laterally away from or external of the edge 12c
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