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Home MEMS Method-of-making-toroidal-MRAM-cells

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 Method of making toroidal MRAM cells

Details
Inventors: Sharma, Manish;
Assignee: Hewlett-Packard Development Company, L.P. (Houston, TX)
Primary Examiner: Le; Thao P.
Assistant Examiner:
Attorney, Agent or Firm:

This invention provides a method of making nano-scaled toroidal magnetic memory cells, such as may be used, for example, in magnetic random access memory (MRAM). In a particular embodiment a semiconductor wafer substrate is prepared and a conductor layer is provided upon the wafer. A hard layer is deposited upon the first conductor. From the hard layer, ion etching is employed to form an annular wall about a pillar, the wall and pillar defining an annular slot. A ferromagnetic data layer is deposited within the annular slot and a junction stack is then provided upon at least a portion of the data layer. A dielectric is applied to insulate the structure and then planarized to expose the pillar.

DETAILED DESCRIPTION Before proceeding with the detailed description, it is to be appreciated that the present invention is not limited to use or application with a specific type of magnetic memory.
Thus, although the present invention is, for the convenience of explanation, depicted and described with respect to typical exemplary embodiments, it will be appreciated that this invention may be applied with other types of magnetic memory.
Referring now to the drawings, FIGS.
1 through 5 conceptually illustrate a method of making a toroidal magnetic memory cell, illustrated in completed form as toroidal magnetic memory cell 512 in FIGS.
5C & 5D), such as may be used in magnetic random access memory (MRAM), according to an embodiment of the present invention.
It will be appreciated that the described process need not be performed in the order in which it is herein described, but that this description is merely exemplary of one preferred method of fabricating toroidal magnetic memory cell 512.
The description of the memory cell as a toroidal magnetic memory cell 512 is based upon the substantially annular nature of the data layer.
In at least one embodiment, the fabrication process may be commenced upon a semiconductor substrate wafer 100.
Typically, the wafer 100 is chemically cleaned to remove any particulate matter, organic, ionic, and or metallic impurities or debris which may be present upon the surface of the wafer 100.
As shown in FIG.
1A, a first conductor layer 102 is deposited upon a semiconductor substrate wafer 100.
The deposition of the conductor layer 102 may be by sputtering, ion beam deposition, electron beam evaporation, or such other appropriate method.
In certain applications, the resulting toroidal magnetic memory cell 512 shown in FIGS.
5C & 5D may be joined to a common conductor.
Access of a particular toroidal magnetic memory cell 512 may then be accomplished by the use of an articulating nanoprobe that provides at least one additional conductor to the top of toroidal magnetic memory cell 512



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