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Method of manufacturing a precision integrated resistor
| Details |
Inventors: Jimenez, Jean;
Assignee: SGS-Thomson Microelectronics, S.A. (Gentilly Cedex, FR)
Primary Examiner: Chaudhuri; Olik
Assistant Examiner: Mulpuri; S.
Attorney, Agent or Firm: Groover; Robert
A precision resistor, on a semiconductor substrate, formed by using two polysilicon stripes to mask the oxide etch (and ion implantation) which forms a third conductive stripe in a moat (active) area of the substrate. The sheet resistance R.sub.p and a patterned width W.sub.p of the polysilicon stripes and the patterned width W.sub.M and sheet resistance R.sub.M, are related as R.sub.p W.sub.p =2R.sub.M W.sub.M. By connecting the three stripes in parallel, a net resistance value is achieved which is independent of linewidth variation. |
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DETAILED DESCRIPTION What is claimed is: 1.
An integrated circuit fabrication method, comprising the steps of: (a.
) providing a substrate which includes at least one substantially monolithic body of semiconductor material; (b.
) forming an insulating layer, in a substantially desired pattern, over portions of said monolithic body of semi-conductor material; (c.
) forming a resistive material over portions of said insulating layer; (d.
) etching said resistive material in a desired pattern to form first and second elongated strips defining an elongated gap therebetween; (e.
) etching said insulating layer, using an anisotropic etch which is selective to said resistive material, under said elongated gap; (f.
) implanting dopant atoms of conductive impurity into said monolithic body of semiconductor material under said elongated gap, to form a third elongated conductive strip; and (g.
) connecting said first, second, and, third elongated strips electrically in parallel, to provide a precision resistor; wherein said implanting step and said step of etching said resistive material are performed with process parameters such that the width W.
sub.
P and eventual sheet resistance R.
sub.
P of each of said first and second elongated strips, the width W.
sub.
M of said elongated gap, and the eventual sheet resistance R.
sub.
M of said monolithic body under said elongated gap, are related approximately as R.
sub.
P W.
sub.
P =2R.
sub.
M W.
sub.
M.
2.
The method of claim 1, wherein said monolithic body consists essentially of silicon.
3.
The method of claim 1, wherein said step of implantation applies a dose and energy such that the TCR (temperature coefficient of resistance) of all of said strips is equal within a factor of 2.
4.
The method of claim 1, wherein said step of implantation applies phosphorus.
5.
The method of claim 1, wherein said step of implantation applies more than 10.
sup.
16 cm.
sup.
-2 of dopant ions.
6.
The method of claim 1, wherein said step of implantation applies N-type dopant ions.
7.
The method of claim 1, wherein said substrate consists essentially of silicon, and said monolithic body is an epitaxial layer of silicon on said substrate
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MEMS 
