Method of vacuum packaging a semiconductor device assembly

DETAILED DESCRIPTION Accordingly, it is an object of the present invention to provide a semiconductor chip device package having a vacuum within interconnect voids in the semiconductor chip device to reduce the interconnective RC delay and prevent metal corrosion.
Another object of the present invention is to provide a low cost packaging technology which changes the dielectric k-value to reduce the interconnective RC delay and prevent metal corrosion.
Yet another object of the present invention is to provide a method of forming a packaged semiconductor assembly by drawing a vacuum on an entire air gap semiconductor device to form a vacuum within the voids separating the interconnects.
A further object of the present invention is to provide a semiconductor chip device package having a vacuum within interconnect voids in the semiconductor chip device to lower the interlevel dielectric constant to reduce the signal propagation delays and enhance the system performance.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner.
Specifically, a semiconductor chip device package is comprised of a semiconductor substrate having semiconductor devices formed on the semiconductor substrate.
At least one dielectric layer is over the semiconductor substrate.
At least one layer of interconnects is over the semiconductor devices and within the at least one respective dielectric layer with at least a portion of the interconnects being separated by voids having a vacuum or air therein.
A passivation layer is over the uppermost of the at least one layer of interconnects.
Wherein the semiconductor chip device is vacuum sealed within a semiconductor chip device package.