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Monolithic in-based III-V compound semiconductor focal plane array cell with single stage CCD output
| Details |
Inventors: Fossum, Eric R.; Cunningham, Thomas J.; Krabach, Timothy N.; Staller, Craig O.;
Assignee: The United States of America as represented by the Administrator of the (Washington, DC)
Primary Examiner: Ngo; Ngan V.
Assistant Examiner:
Attorney, Agent or Firm: Kusmiss; John H., Jones; Thomas H., Miller; Guy M.
A monolithic semiconductor imager includes an indium-based III-V compound semiconductor monolithic active layer of a first conductivity type, an array of plural focal plane cells on the active layer, each of the focal plane cells including a photogate over a top surface of the active layer, a readout circuit dedicated to the focal plane cell including plural transistors formed monolithically with the monolithic active layer and a single-stage charge coupled device formed monolithically with the active layer between the photogate and the readout circuit for transferring photo-generated charge accumulated beneath the photogate during an integration period to the readout circuit. The photogate includes thin epitaxial semiconductor layer of a second conductivity type overlying the active layer and an aperture electrode overlying a peripheral portion of the thin epitaxial semiconductor layer, the aperture electrode being connectable to a photogate bias voltage. |
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DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG.
1 illustrates a focal plane cell embodying the present invention.
Photons entering through a photogate 1 generate charge which is collected in a potential well under the photogate 1 bounded by a potential barrier under an isolation gate 3.
A transfer gate 5 and a screen gate 7 operate in the manner of a single CCD stage to transfer the charge collected under the photogate 1 at the end of an integration period to a potential well under a collector 9.
The resulting change in potential of the collector 9 provides a precise measure of the amount of charge collected under the photogate 1 during the preceding integration period.
The collector 9 is connected to the source of a reset transistor T1 and to the gate of an output transistor T2.
The drains of the two transistors T1, T2 are connected to a +3 volt D.
C.
supply source.
A reset signal applied to the gate of the reset transistor T1 resets the potential of the collector 9 to +3 volts at the beginning of each integration period.
The output of the cell is the source of the output transistor T2.
The single stage CCD operation of the cell of FIG.
1 is illustrated in the sequence of FIGS.
2A through 2D showing the change in the potentials beneath the various gates 1, 3, 5, 7 and beneath the collector 9.
Throughout this sequence, the isolation gate 3 is constantly held at ground potential (i.
e.
, 0 volts), the photogate 1 is constantly held at a potential of +2 volts while the screen gate 7 is constantly held at a potential of about +2.
5 volts.
Initially, at the beginning of the integration period, the collector 9 is reset to +3 volts by the reset signal applied to the gate of the reset transistor T1 while the transfer gate is held at +0.
5 volts.
As shown in FIG.
2A, this forms a potential well beneath the photogate 1.
During the ensuing integration period, photons incident on the top surface of the photogate 1 produce charge carriers which are collected in the potential well beneath the photogate 1 as shown in FIG
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MEMS 
