Multi-layered gate for a CMOS imager

DETAILED DESCRIPTION The present invention provides a multi-layered gate stack process for use in fabricating a pixel sensor cell.
The multi-layered gates have multiple layers including a conductive laver, an optional silicide layer, and an insulating layer, all of which are patterned and etched simultaneously over a first insulating layer.
Also provided are methods for forming the multi-layered gates of the present invention, and a process that achieves high yield overlap process for a photogate--transfer gate overlap that does not require the n-doped region 26.
The combination of a multi-layered gate and an overlapping gate may be a multi-layered transfer gate with an overlapping photogate, a multi-layered photogate with an overlapping transfer gate, a multi-layered source follower gate with an overlapping row select gate, a multi-layered row select gate with an overlapping source follower gate, or any other suitable combination.
Additional advantages and features of the present invention will be apparent from the following detailed description and drawings which illustrate preferred embodiments of the invention.