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Novel high-speed integrated heterostructure transistors, photodetectors, and optoelectronic circuits
| Details |
Inventors: Shur, Michael; Simmons, John G.;
Assignee: Regents of the University of Minnesota (Minneapolis, MN)
Primary Examiner: Edlow; Martin H.
Assistant Examiner:
Attorney, Agent or Firm: Kinney & Lange
A high-speed heterostructure planar integrated circuit includes a planar photodetector together with a transistor (either a Modulation-Doped Field Effect Transistor or a lateral p-n-p bipolar transistor). The planar photodetector includes a bottom confinement layer of a wide bandgap material, a heavily doped first conductivity-type buried layer over the bottom confinement layer, a relatively undoped higher index of refraction layer overlying the buried layer, a top confinement layer of wider bandgap material which has a lower index of refraction, a first vertical contact region of first conductivity type which extends downward to make electrical contact with the buried layer, and a second contact region of second conductivity type spaced laterally from the first contact region and extending through the top confinement layer and a portion of the undoped layer. As a result of the difference in refractive indices of undoped versus doped regions and in wide gap versus narrow gap material, light directed into one end of the photodetector is confined both laterally and vertically to the undoped layer where it is absorbed. Charge separation occurs with first conductivity carries being collected at the first contact region and the buried layer, and second conductivity carriers being collected at the second contact region. |
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DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The basic multilayer structure for the integrated heterojunction optoelectronic device of the present invention is illustrated in FIG.
1.
For purposes of illustration, the heterojunction structure shown in FIG.
1 makes use of a wider bandgap material (AlGaAs) and a narrower bandgap of material (GaAs).
Other heterojunction structures using other semiconductor materials are, of course, within the scope of the present invention.
In FIG.
1, the multilayer structure includes (from bottom up) semi-insulating GaAs substrate 10, AlGaAs bottom confinement layer 12, p+ GaAs buried layer 14, relatively undoped (i.
e.
either undoped or lightly doped) GaAs layer 16, and a top confinement region formed by undoped AlGaAs spacer layer 18, and n+ AlGaAs layer 20.
FIG.
2 shows an integrated planar photodetector 30, which we call a modulation-doped field effect photodetector (MODFED) formed in the structure of FIG.
1.
MODFED 30 shown in FIG.
2 includes first p+ vertical contact region 32 which extends down through layers 20, 18, and 16 and makes electrical contact with buried layer 14.
Second n+ contact region 34 is spaced laterally from region 32 and extends down through layers 20 and 18, and into layer 16.
The bottom of n+ region 34, however, is separated from p+ buried layer 14 by a portion of undoped layer 16.
MODFED 30 is a three terminal device.
Cathode 36 is connected to p+ region 32, anode terminal 38 is connected to n+ region 34, and gate terminal 40 is connected to n+ AlGaAs layer 20.
Also shown in FIG.
2 is an energy band diagram for MODFED 30 in an unbiased state (i.
e.
no bias potential is applied to anode terminal 38, cathode terminal 36, or gate terminal 40).
As illustrated in FIG.
2, holes which are generated by absorption of radiation in undoped layer 16 are collected by vertical p+ contact region 32 and buried p+ layer 14.
Electrons are collected at n+ contact region 34.
MODFED 30 is a planar device.
Light enters directly into GaAs layer 16 under gate 40 and is absorbed in layer 16 while propagating under gate 40 along the gate width (which is the direction perpendicular to the plane in the section shown in FIG
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MEMS 
