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Process for integration of a high dielectric constant gate insulator layer in a CMOS device
| Details |
Inventors: Wang, Ming-Fang; Chen, Chien-Hao; Yao, Liang-Gi; Chen, Shih-Chang;
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. (Hsin-Chu, TW)
Primary Examiner: Prenty; Mark V.
Assistant Examiner:
Attorney, Agent or Firm: Haynes and Boone, LLP
A CMOS device structure, and a method of fabricating the CMOS device, featuring a gate insulator layer comprised of a high k metal oxide layer, has been developed. The process features formation of recessed, heavily doped source/drain regions, and of vertical, polysilicon LDD spacers, prior to deposition of the high k metal oxide layer. Removal of a silicon nitride shape, previously used as a mask for definition of the recessed regions, which in turn are used for accommodation of the heavily doped source/drain regions, provides the space to be occupied by the high k metal oxide layer. The integrity of the high k, gate insulator layer, butted by the vertical polysilicon spacers, and overlying a channel region provided by the non-recessed portion of the semiconductor substrate, is preserved via delayed deposition of the metal oxide layer, performed after high temperature anneals such as the activation anneal for heavily doped source/drain regions, as well as the anneal used for metal silicide formation. |
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DETAILED DESCRIPTION It is an object of this invention to fabricate a complimentary metal oxide semiconductor (CMOS) device featuring a high k dielectric layer for use as a gate insulator layer.
It is another object of this invention to integrate a high k, metal oxide, gate layer, into a CMOS fabrication sequence, after high temperature source/drain anneals, and high temperature metal suicide layer formation procedures, have been performed.
It is still another object of this invention to form the high k, metal oxide gate layer in a space surrounded by lightly doped source/drain (LDD), silicon spacers, wherein the space was created by removal of a silicon nitride masking shape, which in turn is used to define recessed source/drain regions as well as to define word lines.
In accordance with the present invention a method of integrating the formation of a high k, gate insulator layer into a CMOS fabrication procedure, at a stage of the CMOS fabrication procedure after which high temperature procedures have already been performed, is described.
After formation of an N well, and of a P well region, for accommodation of P channel (PMOS), and N channel (NMOS), devices, a silicon nitride shape is formed on the surface of the well regions and used as a mask to selectively remove, and recess, unprotected silicon regions.
Heavily doped P type, and N type, source/drain regions are then formed in the recessed portions in the P and N well regions, via ion implantation and annealing procedures, used to activate the implanted ions.
Deposition of in situ doped polysilicon layers, and dry etching procedures, result in the formation of P type, and N type, lightly doped source/drain (LDD), spacers, on the sides of the silicon nitride shapes, as well as on the sides of the non-recessed silicon shapes, underlying the silicon nitride masking shapes.
Metal silicide regions are next formed in portions of both the P type, and N type heavily doped source/drain region, via formation of a metal shape followed by anneal procedure
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MEMS 
