 Energy beam patterning of protective layers for semiconductor devices |
| According to the present invention, a method for forming resist or other protective patterns on a ... |
|
| Quantum efficiency improvements in active pixel sensors |
| The present invention describes a technique that improves quantum efficiency in a CMOS sensor. This ... |
|
| Pixel cell with high storage capacitance for a CMOS imager |
| The present invention provides a source follower gate with improved storage capacitance formed in a ... |
|
| Image scanning circuitry with row and column addressing for use in electronic cameras |
| OF A PREFERRED EMBODIMENT Those of ordinary skill in the art will realize that the following ... |
|
| Method for manufacturing an optical module and optical module |
| The present invention provides for an improved method for manufacturing an optical module as ... |
|
| Process for manufacture of microoptomechanical structures |
| Inherent thin film properties of materials limit many surface micromachining processes. For example,... |
|
| Piezoelectric on semiconductor-on-insulator microelectromechanical resonators |
| Embodiments of the present invention provide piezoelectric resonators. Briefly described, one ... |
|
|
Semiconductor device
| Details |
Inventors: Ishida, Yoshihiro; Ohmori, Yoshinobu; Ikeda, Ienobu; Terashima, Kazuhiko; Toyoda, Takeshi;
Assignee: Citizen Watch Co., Ltd. (Tokyo, JP)
Primary Examiner: Thomas; Tom
Assistant Examiner: Ostrowski; David
Attorney, Agent or Firm: Kanesaka & Takeuchi
In a semiconductor device comprising an IC chip (8) mounted on a circuit substrate (7) and sealed with a molding resin (11), corner resist films (6a, 6b, 6c, 6d) are formed at positions corresponding to a corner A of the IC chip (8) on the circuit substrate (7), and the corner A of the IC chip (8) is bonded to these corner resist films by using a die bond (9). A die pattern (3a) is exposed outside the corner resist films, and a power supply pattern (3b) is so formed to encompass their periphery. The power supply terminal, the die pattern (3a) and the power supply pattern (3b) are connected to the IC chip (8) of the corners of the IC chip is improved and peel is prevented. Furthermore, bonding of a large number of bonding wires for supplying power can be freely made. |
|
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be explained in detail with reference to the drawings.
FIG.
1 and FIG.
2 show the configuration of a first embodiment of the present invention.
FIG.
1 is a plan view of a BGA package.
FIG.
2 is a sectional view of the principal parts of the first embodiment of the present invention shown in FIG.
1.
The same reference numerals designate the same members referred to in the conventional technology.
The semiconductor device of this first embodiment utilizes the conventional technology illustrated in FIG.
7 inasmuch as a thin copper foil is laminated on both sides of a resin substrate 1 and through-holes 2 are formed, after which a copper plated layer is provided by both non-electrolytic plating and electrolytic plating on all surfaces of the resin substrate 1 on both sides.
Next, a plating resist lamination is provided and developed by exposure to light to form a pattern mask, after which die patterns 3, 3a for the IC chip and a power supply pattern 3b and a lead pattern 4 are formed on the upper surface by pattern etching using an etching liquid, and pad electrodes 5 on which solder bumps are provided are formed on the lower surface.
Here, the outer shapes of the die patterns 3, 3a are greater than the outer shape of the IC chip 8.
Further, the die patterns 3, 3a (Vdd) on the upper surface of the resin substrate 1, a power supply pattern 3b (Vss), and a lead pattern 4 are connected to the pad electrode 5 on the lower surface through the through holes 2.
Next, an insulating film is formed on the corner sections corresponding to at least the corner A of the IC chip 8 and on other specified parts on the die patterns 3, 3a.
A development-type liquid solder resist, a thermosetting solder resist (polyimide/epoxy), or an adhesive polyimide tape, or the like can be used as the insulating film, but in this embodiment a development-type liquid solder resist film was formed using a solder resist process
|
| Related patents |
|
|
Optical memory device and a method for manufacturing thereof
It is a major object of the present invention to provide a novel method of manufacturing an optical memory device, particularly such a method which is suitable for mass ...
|
|
|
Semiconductor package and manufacturing method thereof
The present invention was carried out to solve these problems. That is, an object of the present invention is to provide a semiconductor package which is thin, compact ...
|
|
|
Precision spray processes for direct write electronic components
OF THE INVENTION In accordance with the present invention, there are provided methods for direct material deposition on a substrate, said methods comprising: (a) ...
|
|
|
Multiple beams and nozzles to increase deposition rate
OF THE INVENTION A schematic of the preferred embodiment of this invention is given in FIG. 1, showing the position of the invention within a direct material deposition ...
|
|
|
Optical memory device and a method for manufacturing thereof
It is a major object of the present invention to provide a novel method of manufacturing an optical memory device, particularly such a method which is suitable for mass ...
|
|
|
Integrated circuit structure having a flip-chip mounted photoreceiver
In accordance with the present invention, an IC package structure includes a photoreceiver flip-chip mounted to the package substrate in order to provide an IC package ...
|
|
|
High-density electronic package, and method for making same
What is claimed is: 1. An electronic package having contacts adapted to be attached to a substrate, said electronic package comprising: at least one electronic device, ...
|
|
|
Forming structures from CAD solid models
The present invention pertains generally to a class of material deposition processes that use a laser to heat and, subsequently, fuse powder materials into solid layers. ...
|
|
|
Stereolithographically fabricated conductive elements, semiconductor device components and assemblies including such conductive elements, and methods
The present invention includes stereolithographically fabricated conductive elements. Accordingly, the conductive elements of the present invention may have one or more ...
|
|
|
Interposer and methods for fabricating same
OF THE INVENTION The Interposer FIGS. 1, 1A, 1B, and 2 depict an exemplary interposer 100 of the present invention. Interposer 100 includes an interposer substrate 110 ...
|
|
|
MEMS 
