Semiconductor device with upper portion of plugs contacting source and drain regions being a first self-aligned silicide

DETAILED DESCRIPTION Accordingly, it is an object of the present invention to solve the aforementioned problem of the conventional techniques, and to provide a semiconductor device capable of simultaneously decreasing the wiring resistance and increasing the charge-storage capacity.
In order to achieve the aforementioned object, according to an embodiment of the present invention, a semiconductor device is proposed, the semiconductor device including: a cell transistor including: a pair of source and drain regions formed in a surface portion of a silicon substrate so as to have a predetermined space therebetween; a channel region sandwiched by the source and drain regions; a gate formed above the channel region with a gate dielectric film being formed therebetween; and silicon plugs formed on the silicon substrate, the silicon plugs electrically contacting the source and drain regions, an upper portion of the silicon plug being a first self-aligned silicide portion.
Furthermore, in order to achieve the aforementioned object, according to another embodiment of the present invention, a method of manufacturing a semiconductor device is proposed, the method including: forming a pair of source and drain regions on a silicon substrate with a predetermined space being held therebetween; forming a gate on a channel region sandwiched by the source and drain regions with a gate dielectric film provided between the channel region and the gate; and changing an upper portion of the silicon plugs thus formed to a self-aligned silicide.