Semiconductor memory device including Shadow RAM

DETAILED DESCRIPTION It is an object of the invention to provide a semiconductor memory apparatus for preventing an increase in a cell area of a memory cell of a Shadow RAM and achieving high capacity formation of a storage capacitor.
Further, it is an object of the invention to provide a semiconductor memory apparatus capable of designing a Shadow RAM by utilizing design data of a wiring layer of a transistor applied to an SRAM which has been generally used conventionally, as it is.
Further, it is an object of the invention to provide a semiconductor memory apparatus achieving a reduction in a number of steps of design of a Shadow RAM and shortening of a design period of time and having a large storage capacity.
A semiconductor memory apparatus according to the invention includes an SRAM memory cell and a Shadow RAM memory cell.
The Shadow RAM memory cell is provided with a ferroelectric capacitor at the SRAM memory cell and is constituted such that an area of the Shadow RAM memory cell is equal to an area of the memory cell of SRAM.
Further, a semiconductor memory apparatus according to the invention at least includes a Shadow RAM having a ferroelectric capacitor at an SRAM memory cell, the Shadow RAM includes a relay wiring layer and two storage nodes of a portion of the SRAM memory cell is connected to the low electric capacitor respectively via a relay wiring of the relay wiring layer and an opening portion.
The respective storage nodes and the relay wiring of the relay wiring layer are connected via a first and a second opening portion and the relay wiring and a lower electrode of the ferroelectric capacitor are connected via a third and a fourth opening portion.
The relay wiring is provided to make a distance between the third and the fourth opening portions narrower than the distance between the first and the second opening portions.
That is, the relay wiring layer is provided, the relay wiring layer is formed with the relay wiring for connecting an upper layer wiring layer and a lower layer wiring layer in an arbitrary pattern shape and a position of an opening portion for connecting the upper layer wiring layer connected to the relay wiring and a position of an opening portion for connecting the lower layer wiring are set to different arbitrary positions