Sog with moisture resistant protective capping layer

DETAILED DESCRIPTION I claim: 1.
A method of planarizing a semiconductor wafer having interconnect tracks metal of formed thereon, comprising applying a layer of inorganic spin-on glass to the wafer, curing said spin-on glass at a temperature not exceeding about 450.
degree.
C.
, then placing the wafer in a dielectric deposition chamber, subjecting the wafer to in situ disconnection and outgassing of water and reaction by-products, and then capping the wafer in a moisture-free environment with a protective dielectric layer resistant to moisture diffusion.
2.
A method as claimed in claim 1, wherein said metal is aluminum.
3.
A method as claimed in claim 1, wherein the SOG is a phosphorus-alloyed SOG.
4.
A method as claimed in claim 1, wherein that said dielectric capping layer is selected from the group consisting of: phosphosilicate glass; Borosilicate glass, Si.
sub.
w O.
sub.
x B.
sub.
y H.
sub.
z ; Arsenosilicate glass, Si.
sub.
w O.
sub.
x As.
sub.
y H.
sub.
z ; Lead silicated glass, Si.
sub.
w O.
sub.
x Pb.
sub.
y H.
sub.
z ; Silicon nitride, Si.
sub.
x N.
sub.
y H.
sub.
z ; Silicon oxynitride, Si.
sub.
w N.
sub.
x O.
sub.
y H.
sub.
z ; Fluorinated silicon nitride, Si.
sub.
w N.
sub.
x F.
sub.
y H.
sub.
z ; and Florinated silicon oxynitride, Si.
sub.
v N.
sub.
w O.
sub.
x F.
sub.
y H.
sub.
z.
5.
A method as claimed in claim 1, wherein it the wafer is fabricated in the following manner: a) a first layer of interconnect metal is deposited on the wafer; b) said first layer is etched to leave the desired interconnect track pattern; c) a first layer of dielectric is deposited over the etched interconnect tracks; d) one or more layers of spin-on glass is applied over the first layer of dielectric to planarize said first dielectric layer; e) disconnection and outgassing of water and its by-products is performed; d) a protective, moisture diffusion resistant dielectric capping layer is deposited; e) contact holes are opened through the deposited layers to reach the first interconnect layer while the wafers are held in a moisture-free environment to prevent water pick-up through these holes; f) a second layer of interconnect metal is applied; and g) the second layer of interconnect metal is etched in the desired pattern